Multilayer Connection Structure for 3D Stacked IC Interconnects
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Solution Overview
Problem
Conventional three-dimensional stacked memory devices require multiple masks and etching steps for each contact level, leading to increased costs and complexity due to the need for separate masks for each contact level, which limits the efficiency and scalability of interconnect formation.
Innovation Solution
A method is introduced to reduce the number of masks and etching steps by using a set of N etch masks to create interconnect contact regions across multiple levels, where each mask is used to etch specific levels, allowing for the formation of contact openings up to and including 2N contact levels, and electrical conductors are formed through these openings to connect landing areas across the stack, with additional masks used to optimize the process for different sets of contact openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masks are used for each contact level, then each contact level can be precisely etched, but the number of masks and etching steps increases significantly
Solution Approach 1:
A single mask pattern is designed to serve multiple contact levels simultaneously. The mask defines etch openings that align with landing areas across different contact levels (e.g., contact levels 18.2, 18.4, 18.6, 18.8), allowing one mask to perform the function of multiple separate masks would traditionally require
Solution Approach 2:
The etching process is segmented into multiple sequential steps, where different masks are applied at different stages to etch different contact levels. For example, first mask 91 is used to etch contact levels 18.2 and 18.4, then mask 92 is used to etch contact levels 18.6 and 18.8, dividing the complex multi-level etching into manageable segments
2Manufacturing precision
If multiple masks are used for each contact level, then contact openings can be precisely formed, but the manufacturing cost increases
Solution Approach 1:
The patent reduces manufacturing cost by making masks multi-functional. A single mask pattern is used to define etch openings for multiple contact levels, thereby reducing the total number of masks required and the associated manufacturing costs while maintaining precise contact opening formation
Solution Approach 2:
The patent combines the etching operations for multiple contact levels into fewer process steps. By merging the functions of multiple masks into one or two masks, the overall manufacturing process is simplified and cost is reduced
3Reliability
If conventional interconnect structures are used, then each contact level is properly connected, but the footprint required increases
Solution Approach 1:
The patent transitions from a planar interconnect layout to a three-dimensional stacked architecture. Contact levels are arranged vertically in stacks (e.g., contact levels 18.1-18.8 arranged in four stacks of two levels each), allowing interconnects to access multiple levels through vertical openings rather than requiring extensive lateral space
Data Source
AI summary
A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.