Spacer-enabled poly gate for sub-lithographic transistor formation
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Solution Overview
Problem
The reduction in size of patterned polysilicon insulated gates for transistors in semiconductor integrated circuits is limited by current lithographic processes, preventing proportional size decreases with smaller transistors.
Innovation Solution
A method involving the deposition of dielectrics and spacer films on a semiconductor substrate, followed by trench creation and selective etching to form narrow channels, where gate oxides and polysilicon are grown and separated into independent insulated gates, allowing for sub-lithographic pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If lithographic processes are used to form insulated gates, then manufacturing capability is maintained, but gate size reduction is limited
Solution Approach 1:
The process segments the gate formation into multiple steps: first forming a mandrel structure, then depositing spacer material around it, selectively removing portions, and finally forming the gate. This multi-step segmentation allows achieving sub-lithographic dimensions that cannot be obtained through single-step lithography alone.
Solution Approach 2:
The invention transitions from planar 2D lithographic patterning to 3D spacer-based patterning. By depositing conformal spacer layers around vertical mandrels and using selective etching, the process exploits the third dimension (vertical height) to define horizontal feature sizes, enabling dimensions below the lithographic resolution limit.
2Productivity
If transistor size is reduced to increase density, then die efficiency improves, but gate size cannot decrease proportionally due to lithographic limits
Solution Approach 1:
The mandrel structure is formed in advance with dimensions larger than the final gate, and spacers are deposited around it. This preliminary action allows the final gate dimensions to be defined by the spacer thickness rather than direct lithography, enabling smaller features while maintaining manufacturing capability.
Solution Approach 2:
The spacer material acts as an intermediary between the lithographically-defined mandrel and the final gate structure. The spacer's conformal deposition and selective removal allow precise control of gate dimensions without being constrained by lithographic resolution, serving as a mediator that translates larger mandrel features into smaller final gate features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of smaller insulated gates without the limitations of traditional lithographic processes, facilitating the miniaturization of transistors and improving semiconductor die efficiency.
Implementation Method 1
depositing a spacer film on the first dielectric including walls and a bottom of the at least one trench
Implementation Method 2
growing gate oxides on exposed faces of the semiconductor substrate at the bottoms of the at least two narrow channels
Implementation Method 3
depositing polysilicon on the faces of the first and second dielectrics and into the at least two narrow channels
Data Source
AI summary
A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors.