Raised Source/Drain CMOS Active Pixel Sensor Leakage Reduction
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Solution Overview
Problem
Conventional CMOS image sensor technologies face challenges in achieving shallow source/drain junctions without increased leakage, as shallow junctions lead to silicon loss during contact etching, necessitating deeper junctions for adequate isolation, which increases device area and leakage.
Innovation Solution
The formation of raised source/drain regions in CMOS active pixel sensor cells through a dry-by-wet etch process and thermal annealing, where doped polysilicon is used to extend the source or drain regions into the semiconductor body, creating shallow junctions without leakage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If shallow source/drain junctions are formed, then device area is reduced, but leakage increases due to silicon loss during contact etching
Solution Approach 1:
The source/drain structure is elevated from the substrate plane to form raised regions above the channel, transitioning from a 2D planar junction to a 3D vertical structure. This dimensional change allows the junction to remain shallow in the substrate while providing adequate isolation through the raised portion, resolving the contradiction between small area and low leakage.
Solution Approach 2:
The source/drain regions are formed and elevated before contact etching operations. By establishing the raised structure in advance, the silicon loss during subsequent contact etching is prevented, as the elevated regions provide inherent protection and definition for the contact areas.
2Reliability
If deeper source/drain junctions are formed to prevent silicon loss, then leakage is reduced, but device area increases
Solution Approach 1:
Instead of increasing junction depth in the vertical substrate direction, the solution elevates the source/drain regions above the channel plane. This redirects the isolation mechanism from depth-based to height-based, maintaining shallow substrate junctions while achieving adequate leakage prevention through the raised structure's geometric definition.
Solution Approach 2:
The source/drain structure is segmented into two functional portions: a shallow junction region embedded in the substrate that minimizes area, and a raised extension above the channel that provides isolation and protection. This segmentation allows each portion to optimize for its specific function without compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced leakage from 0.1 pA to tens of fA, relaxing junction isolation requirements and minimizing device area, while maintaining shallow junctions.
Implementation Method 1
A region of the semiconductor body that has been doped to an opposite doping type of the channel region by diffusion of dopants from the doped polysilicon extends the source or drain from the doped polysilicon to border the channel region.
Implementation Method 2
Thermal annealing diffuses some of the dopants into the semiconductor body.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated circuit having a device. The device has a first raised source/drain area arranged over a first source/drain region of a substrate, and a second raised source/drain area arranged over a second source/drain region of the substrate. A first gate stack has a dielectric layer positioned over the substrate and an overlying conductive layer. The first gate stack is laterally between the first raised source/drain area and the second raised source/drain area. Sidewall spacers are located over the dielectric layer and laterally between the first gate stack and the first raised source/drain area and the second raised source/drain area.