Fin-Shaped Semiconductor Layer Formation in Surrounding Gate Transistors
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Solution Overview
Problem
The challenge in producing semiconductor devices, particularly Surrounding Gate Transistors (SGTs), lies in suppressing leak current and reducing circuit area while managing the complexity of multiple masks and high-temperature processes, which complicates the formation of fin-shaped and pillar-shaped semiconductor layers and gate structures.
Innovation Solution
A method employing a gate last process using two masks to form a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, and a gate electrode, with specific steps involving polysilicon deposition, etching, and insulating film formation to create a SGT structure that reduces the number of steps and prevents misalignment, allowing for efficient metal-gate formation and diffusion layer formation in the upper portion of the pillar-shaped semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three masks are used to form the silicon pillar, planar silicon layer, and gate line separately, then each component can be precisely formed, but the production process becomes complex and time-consuming
Solution Approach 1:
The patent combines the formation of the silicon pillar, planar silicon layer, and gate line into a single etching step using one mask pattern. The mask is designed with specific geometric features that enable self-aligned etching, where the etch process automatically creates all three structures simultaneously with precise dimensional control, eliminating the need for three separate masking and etching operations.
Solution Approach 2:
The single mask serves multiple functions by incorporating different geometric patterns in different regions. The same mask structure enables the formation of vertical silicon pillars, planar silicon layers, and gate lines through a unified etching process, making the mask a multi-functional element that defines all three critical structures.
2Manufacturing precision
If metal is deposited to fill a hole with upper portion narrower than lower portion, then the upper portion is filled first, but the lower portion remains unfilled
Solution Approach 1:
The patent inverts the traditional approach by forming the gate structure with the metal layer deposited before the insulating layer is fully formed. Specifically, the metal is deposited to create an inverted tapered shape, then the insulating layer is deposited and planarized to expose the metal, ensuring complete filling from the bottom up rather than leaving voids at the narrower upper portion.
Solution Approach 2:
The metal layer is deposited in advance with a predetermined inverted tapered profile before the final planarization step. This preliminary metal deposition with controlled geometry ensures that when the insulating layer is added and planarized, the metal remains fully contained and connected, preventing any unfilled regions.
3Object-affected harmful factors
If a first insulating film is formed around the fin-shaped semiconductor layer and subjected to etch back, then parasitic capacitance between gate line and substrate is decreased, but additional process steps are required
Solution Approach 1:
The patent merges the formation of the first insulating film around the fin-shaped semiconductor layer with the gate structure fabrication process. The same insulating film that provides parasitic capacitance reduction is also used as part of the gate structure, eliminating the need for separate etch-back processes and integrating multiple functions into a unified process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the SGT production process by reducing the number of masks and steps, preventing partial filling of metal in the gate structure, and enabling effective insulation and contact formation, thereby improving the integration density and reducing parasitic capacitance.
Implementation Method 1
depositing a first polysilicon on the second insulating film, planarizing the first polysilicon
Implementation Method 2
etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon
Implementation Method 3
depositing a second polysilicon around the fourth insulating film, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask
Implementation Method 4
depositing a first metal, and forming a gate electrode and a gate line
Data Source
AI summary
An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.