Doped Layer Reduces Transistor Resistance
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Solution Overview
Problem
Fin-based transistors, including tri-gate and Gate-All-Around devices, face increased external resistance as fin width decreases, leading to reduced drive current and higher off-state leakage current.
Innovation Solution
The use of doped layers, such as delta-doped or pulse-doped layers, beneath the source and drain regions with a shallow recess, reduces external resistance without the need for deep recessing, and improves charge supply by controlling doping depth and distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fin thickness is reduced to improve short-channel effects, then sub-threshold gradient and DIBL are improved, but external resistance increases
Solution Approach 1:
The patent applies local quality by creating a doped layer with different doping concentration specifically in the source/drain regions where high conductivity is needed, while maintaining the intrinsic fin structure elsewhere. The doped layer is localized to regions adjacent to the channel, providing high carrier concentration locally to reduce external resistance without affecting the overall fin thickness that controls short-channel effects.
Solution Approach 2:
The patent uses composite materials by combining the intrinsic semiconductor fin material with a separately formed doped layer. This creates a composite structure where the undoped fin maintains proper threshold voltage and short-channel characteristics, while the doped layer provides additional carriers to reduce external resistance in the source/drain regions.
2Object-affected harmful factors
If deep recessing is performed to reduce external resistance, then source/drain resistance decreases, but off-state leakage current increases
Solution Approach 1:
The patent changes the doping parameter by introducing a doped layer with high carrier concentration in the source/drain regions. This increases the electrical conductivity and reduces external resistance without requiring deep recessing that would expose more of the fin structure and increase leakage current.
3Reliability
If the fin thickness is reduced to improve short-channel effects, then DIBL decreases, but drive current decreases due to increased external resistance
Solution Approach 1:
The patent applies local quality by creating a doped layer with different doping concentration specifically in the source/drain regions where high conductivity is needed, while maintaining the intrinsic fin structure elsewhere. The doped layer is localized to regions adjacent to the channel, providing high carrier concentration locally to reduce external resistance without affecting the overall fin thickness that controls short-channel effects.
Solution Approach 2:
The patent uses composite materials by combining the intrinsic semiconductor fin material with a separately formed doped layer. This creates a composite structure where the undoped fin maintains proper threshold voltage and short-channel characteristics, while the doped layer provides additional carriers to reduce external resistance and improve drive current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers source/drain resistance and off-state leakage current while maintaining steep sub-threshold gradients, enhancing transistor performance and power efficiency.
Implementation Method 1
a doped layer is formed over the substrate and beneath the channel
Data Source
AI summary
An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.