Multi-Threshold Voltage FETs via Strain Engineering
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Solution Overview
Problem
Existing methods for threshold voltage tuning in III-V CMOS devices, such as doping, gate length tuning, and gate work function tuning, are ineffective or complicated, especially for thin-body FETs like FinFETs and QWFETs, and do not support multiple threshold voltage implementations.
Innovation Solution
The use of strain-induced band shifts in III-V semiconductor materials to manipulate the conduction and valence bands, allowing for the achievement of multiple threshold voltages through lattice mismatch and epitaxy-related band structure engineering, specifically in FinFETs and QWFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel doping is used to tune threshold voltage in thin-body devices, then threshold voltage can be adjusted, but the method is not well-suited for FinFETs and QWFETs
Solution Approach 1:
The patent changes the physical parameter of band structure through strain engineering. By applying mechanical strain to the channel material, the conduction and valence bands are shifted, directly modulating the threshold voltage without requiring doping. This approach is specifically tailored for thin-body devices where doping is ineffective.
Solution Approach 2:
The patent replaces the chemical/doping-based threshold voltage tuning mechanism with a mechanical strain-based mechanism. Instead of introducing dopant atoms to alter electrical properties, mechanical strain is applied to the crystal lattice to achieve band structure modification and threshold voltage control.
2Manufacturing precision
If gate length tuning or gate work function tuning is used to modulate threshold voltage, then threshold voltage can be adjusted for thin-body devices, but the methods are complicated and do not support multiple threshold voltage implementations
Solution Approach 1:
The patent introduces buffers with different lattice constants at specific locations beneath the channel material. Each buffer region is engineered with tailored properties (different lattice constants) to produce the desired strain and threshold voltage in the overlying channel. This localized approach enables multiple threshold voltages without complicating the overall device structure.
3Adaptability or versatility
If strain-induced band shifts are used to achieve multiple threshold voltages, then multiple threshold voltage implementations are enabled, but the approach requires lattice mismatch and epitaxy-related band structure engineering
Solution Approach 1:
The patent performs preliminary strain engineering during the epitaxial growth process. By pre-engineering the buffer layers with appropriate lattice constants before channel formation, the desired strain and threshold voltage characteristics are established early in the manufacturing process, simplifying subsequent fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a viable method for achieving a threshold voltage tuning range of approximately 0.25 to 0.5 volts for n-type FETs and applies to p-type FETs as well, offering a stable and effective solution for multiple threshold voltage implementations without the limitations of traditional methods.
Implementation Method 1
achieve multiple threshold voltages through lattice mismatch and epitaxy-related band structure engineering
Implementation Method 2
The use of strain-induced band shifts in III-V semiconductor materials to manipulate the conduction and valence bands
Implementation Method 3
achieve multiple threshold voltages through lattice mismatch and epitaxy-related band structure engineering
Data Source
AI summary
A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.