ESD Protection Device With Local Doping For Low Trigger Voltage
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Solution Overview
Problem
Conventional ESD protection devices based on MOS transistors face challenges in achieving low trigger voltage and high bearable current, particularly in high voltage applications, with existing designs either improving bearable current at the expense of higher trigger voltage or vice versa.
Innovation Solution
The proposed ESD protection device incorporates a gate structure on a substrate with a drain doped region and a first doped region of a lower impurity concentration, strategically positioned at a distance from the gate, which enhances current shunting and allows for both low trigger voltage and high bearable current by optimizing the impurity concentrations and well structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drain doped region is set separate from the gate structure by a distance to improve bearable current, then the bearable current increases, but the trigger voltage remains high
Solution Approach 1:
The patent applies local quality by creating a first doped region with lower impurity concentration within the drain doped region. This localized modification of doping concentration allows the drain region to have different electrical properties at different locations: the lower impurity concentration area facilitates lower trigger voltage while the overall drain structure maintains high bearable current capability through its separation from the gate.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a first doped region with lower impurity concentration than the main drain doped region. This parameter change in the local area affects the electric field distribution and carrier concentration, enabling reduced trigger voltage while maintaining the structural separation that provides high bearable current.
2Ease of manufacture
If the conventional MOS transistor structure is used for ESD protection, then the device is simple to manufacture, but neither low trigger voltage nor high bearable current is achieved
Solution Approach 1:
The invention maintains the conventional MOS transistor structure for ease of manufacture but introduces a localized modification: a first doped region with lower impurity concentration within the drain region. This local quality change improves ESD protection capability by enabling lower trigger voltage without requiring a complete redesign of the manufacturing process.
Solution Approach 2:
The patent incorporates the first doped region with lower impurity concentration as a preliminary structural feature during device fabrication. This preliminary action of creating the low impurity concentration region before final device operation ensures that the ESD protection device is pre-configured to achieve both low trigger voltage and high bearable current from the outset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces trigger voltage while increasing bearable current, improving the overall ESD protection capability by utilizing a current shunting mechanism and carefully controlled impurity concentrations, thus addressing the limitations of conventional designs.
Implementation Method 1
The first doped region has a second impurity concentration lower than the first impurity concentration... enhances current shunting
Data Source
AI summary
An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.