Buried Cross-Couple Interconnect for Compact SRAM Bit Cells
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Solution Overview
Problem
Existing SRAM bit cell structures with complementary field-effect transistors require complex patterning of semiconductor material for cross-couple connections, leading to increased bit cell size and scalability issues.
Innovation Solution
A buried cross-couple interconnect is formed vertically beneath two field-effect transistors, coupled with the gate electrode of one and the source/drain region of the other, using a method involving sacrificial layers and dielectric/conductor replacements to eliminate the need for complex patterning and enable self-aligned gate cuts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-couple connections are implemented by extending gate electrodes and connecting with source/drain regions using metallization in the overlying interconnect structure, then the SRAM bit cell can function properly, but the patterning of semiconductor material becomes complex and the bit cell size increases
Solution Approach 1:
The patent moves the cross-couple interconnect from the lateral plane to the vertical dimension by forming it as a buried structure beneath the source/drain regions. This dimensional transition eliminates the need for complex lateral patterning of source/drain regions to create cross-couple connections, as the interconnect is formed in the vertical subsurface region instead.
Solution Approach 2:
The patent introduces a buried cross-couple interconnect as an intermediary element that mediates the connection between gate electrodes of adjacent transistors. This intermediary structure is formed in the subsurface region and provides the cross-couple functionality without requiring direct lateral connection through patterned source/drain regions or overlying metallization.
2Reliability
If cross-couple connections are implemented by extending gate electrodes and connecting with source/drain regions using metallization in the overlying interconnect structure, then the SRAM bit cell can function properly, but the bit cell size becomes larger
Solution Approach 1:
By forming the cross-couple interconnect in the vertical dimension beneath the source/drain regions rather than in the lateral plane, the patent reduces the lateral footprint of the bit cell. The buried interconnect structure utilizes the vertical subsurface space, thereby compacting the overall bit cell area.
3Device complexity
If sacrificial layers are replaced with dielectric material and the third sacrificial layer is replaced with conductor to form buried cross-couple interconnect, then the complexity of cross-couple connections is reduced, but additional fabrication steps are required
Solution Approach 1:
The patent performs preliminary actions by forming multiple sacrificial layers in specific positions before final device assembly. These sacrificial layers are strategically placed to define the future locations of dielectric regions and the buried cross-couple interconnect, enabling subsequent self-aligned formation of the interconnect structure.
Solution Approach 2:
Sacrificial layers serve as intermediary structures during fabrication that temporarily occupy spaces needed for the final device architecture. By replacing these sacrificial layers with appropriate materials (dielectric or conductor), the patent enables formation of the buried cross-couple interconnect with reduced lateral patterning complexity.
Data Source
AI summary
Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A buried cross-couple interconnect is arranged in a vertical direction beneath a first field-effect transistor and a second field-effect transistor. The buried cross-couple interconnect is coupled with a gate electrode of the first field-effect transistor, and the buried cross-couple interconnect is also coupled with a source/drain region of the second field-effect transistor.