SRAM Vertical Transistor Stacking for Integration Density
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Solution Overview
Problem
Current SRAM devices lack efficient integration and operational speed due to the limitations in transistor configuration and manufacturing processes, particularly in achieving a stacked structure that enhances electrical characteristics and reduces the number of masks required.
Innovation Solution
The SRAM device incorporates first transistors operating horizontally and second transistors configured to operate vertically, with vertical gates and channels, and a method of manufacturing that involves forming semiconductor layers on a second substrate, stacking them on a first substrate, and patterning to create vertical pillars surrounded by conductive layers, enabling vertical connection and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional horizontal transistor configuration is used, then manufacturing process is simpler, but integration efficiency and operational speed are limited
Solution Approach 1:
The patent transitions from conventional horizontal transistor layout to a vertical transistor configuration where the channel extends in the vertical direction. This dimensional change allows multiple transistors to be stacked vertically, significantly improving integration density and efficiency while maintaining manufacturing feasibility through adapted process steps.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: forming horizontal transistors on a first substrate, preparing semiconductor layers on a second substrate, attaching substrates, and forming vertical structures. This segmentation allows complex vertical transistor integration to be achieved through manageable process steps, resolving the contradiction between improved integration and manufacturing complexity.
2Speed
If vertical transistor configuration is implemented, then operational speed improves, but manufacturing process complexity increases
Solution Approach 1:
Semiconductor layers are prepared and patterned on a separate second substrate before attachment to the first substrate. This preliminary action allows vertical transistor structures to be pre-formed with precise geometry, improving operational speed while simplifying the final assembly process and reducing overall manufacturing complexity.
Solution Approach 2:
The patent employs a stacked configuration where vertical transistors are nested above horizontal transistors, with the vertical channel extending through multiple layers. This nesting approach maximizes space utilization and improves operational speed through enhanced electrical characteristics while managing manufacturing complexity through modular layering.
3Reliability
If stacked transistor structure is used, then electrical characteristics are enhanced, but number of manufacturing masks increases
Solution Approach 1:
The manufacturing process merges the formation of horizontal and vertical transistor structures into an integrated flow where substrates are attached and processed together. This merging approach enables the stacked transistor configuration that enhances electrical characteristics while consolidating mask steps, reducing the total number of masks required compared to separate processing approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical characteristics of transistors, improves integration, and reduces the number of masks needed, leading to improved operational speed and efficiency in SRAM devices.
Implementation Method 1
implanting impurities on a second substrate to form semiconductor layers on the second substrate
Data Source
AI summary
Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be vertically connected to the first transistors. In example embodiments, the second transistors may be vertical transistors that include vertical gates surrounding vertical channels.