ESD Protection Circuit Using Threshold Voltage Detection
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Solution Overview
Problem
Existing ESD protection circuits face challenges in distinguishing between electrostatic discharge events and rapid power-on conditions, leading to false triggering and increased risk of damage to integrated circuits, particularly during simultaneously switching outputs (SSO) events, due to reliance on RC time constants and parasitic components.
Innovation Solution
The proposed ESD protection circuit employs a comparator and latch mechanism with current mirrors and biasing devices to detect electrostatic discharge events independently of RC parasitic components, generating a trigger signal to activate a shunt device, thereby avoiding false triggering and allowing rapid power-on without additional timeout circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If an RC time constant filter is used to distinguish ESD events from nominal signals, then signal differentiation capability is improved, but false triggering occurs during rapid power-on and SSO events
Solution Approach 1:
The patent changes the triggering parameter from RC time constant-based voltage detection to threshold voltage-based detection. The ESD protection circuit triggers when the threshold voltage of the trigger device exceeds a predetermined level, rather than using RC filtering. This parameter change allows the circuit to respond to actual ESD events while ignoring rapid power-on and SSO transients that do not reach the threshold voltage level.
Solution Approach 2:
The patent eliminates the need for complex RC time constant filtering and timeout circuitry by using a simple threshold voltage comparison mechanism. The trigger device itself serves as the detection element, and once triggered, the latch maintains the protection state. This simplifies the circuit structure and reduces false triggering without requiring additional complex components.
2Reliability
If RC time constant is reduced to eliminate false triggering during power-on, then power-on reliability is improved, but differentiation between ESD events and power-on events remains insufficient
Solution Approach 1:
The patent uses threshold voltage as the triggering parameter instead of RC time constant. The trigger device's threshold voltage remains relatively stable during power-on but is exceeded during ESD events. This allows the circuit to maintain reliability during power-on while still detecting ESD events, as the threshold voltage mechanism inherently differentiates between the two conditions based on voltage level rather than time constant.
3Reliability
If additional timeout circuitry is added to release the trigger latch, then false triggering protection is improved, but device complexity and chip area increase
Solution Approach 1:
The patent extracts the timeout function from a separate circuit and integrates it into the latch mechanism itself. The latch naturally maintains the triggered state until the threshold voltage condition is no longer met, eliminating the need for separate timeout circuitry. This reduces device complexity and chip area while maintaining false triggering protection.
Solution Approach 2:
The latch device serves multiple functions: it maintains the triggered state, provides false triggering protection, and eliminates the need for separate timeout circuitry. By making the latch multi-functional, the patent reduces overall circuit complexity while maintaining reliability.
4Device complexity
If RC parasitic components are used for triggering, then triggering mechanism is simpler, but processing variations and chip area expense increase
Solution Approach 1:
The patent changes from using RC parasitic components (which have high processing variation) to using the threshold voltage of a trigger device. Threshold voltage is a more stable parameter with less processing variation. This maintains triggering mechanism simplicity while reducing sensitivity to manufacturing variations and decreasing chip area expense.
Data Source
AI summary
An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.