Flash Memory ASSPC Bit-Line Voltage Control

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Solution Overview

Problem

Existing flash memory devices face challenges in achieving a narrow program threshold voltage (Vt) distribution width while maintaining efficient programming time, particularly in Multi-Level Cell (MLC) devices, where data reliability is compromised due to wide Vt distributions and increased programming time.

Innovation Solution

The Automatic Selective Slow Programming Convergence (ASSPC) method involves incrementing the bit-line (BL) voltage after a pre-program verify (PPV) voltage is reached, allowing for finer control over the programming process by slowing down programming with incremental BL voltage increments, thereby reducing the Vt distribution width without significantly extending overall programming time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional programming methods are used, then programming time is maintained at acceptable levels, but Vt distribution width becomes wide compromising data reliability

Engineering Contradiction:
Improvedata reliabilityVSAvoidVt distribution width
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by making the programming process adaptive and variable. The control circuit dynamically adjusts programming parameters based on real-time detection of Vt levels. When a cell approaches the target Vt range, the system automatically reduces programming current or extends pulse width to achieve precise convergence, thereby narrowing Vt distribution without requiring manual intervention or fixed timing sequences.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback through a detection circuit that continuously monitors the Vt level of programmed cells and provides this information to the control circuit. Based on this feedback, the control circuit adjusts programming parameters in real-time to ensure cells converge to the target Vt range. This closed-loop control mechanism is what enables the system to achieve narrow Vt distribution while maintaining acceptable programming times.

Inventive Principle:
Principle #23Feedback

2Productivity

If programming speed is increased to reduce programming time, then productivity improves, but Vt distribution width increases compromising reliability

Engineering Contradiction:
Improveprogramming speedVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the programming process into distinct phases: an initial rapid programming phase where high current is applied to quickly program most cells, and a final convergence phase where the detection circuit identifies cells needing additional programming and the control circuit applies adjusted parameters to bring these cells to the target Vt. This segmentation allows the system to maintain high overall productivity while ensuring reliability for cells that require precise programming.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by providing enhanced programming convergence only to the subset of cells that detection identifies as needing it. Rather than slowing down the entire programming process, the system applies additional programming current or extended pulse width selectively to only those cells that have not yet reached the target Vt range, thereby maintaining overall programming speed while ensuring reliability where needed.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If multiple programming steps are added to narrow Vt distribution, then manufacturing precision improves, but programming time increases

Engineering Contradiction:
ImproveVt distribution widthVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent makes the programming process dynamic by using a single programming step with variable duration and current levels. The control circuit adjusts the pulse width and current magnitude in real-time based on feedback from the detection circuit. This dynamic adjustment eliminates the need for multiple fixed programming steps, achieving narrow Vt distribution through a single adaptive step rather than through sequential fixed steps.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes programming parameters (current level, pulse width) dynamically during the programming process based on real-time Vt detection. Instead of using fixed parameters for multiple steps, the system continuously monitors Vt and adjusts parameters accordingly. This parameter change approach achieves precise Vt control while minimizing the total time required compared to multiple fixed programming steps.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

ASSPC effectively narrows the Vt distribution width by approximately 50% compared to conventional methods, enhancing data reliability and allowing for more programmed states in MLC devices without substantial increases in programming time, thus improving memory cell performance.

Implementation Method 1

a voltage applied to a bit line, coupled to the selected memory cell, will be incremented

Methodology Applied
Scientific EffectElectrical conduction control: Conduction (electrical)

Data Source

PatentUS8638612B2Automatic selective slow program convergence
Publication Date: 2014.01.28 MICRON TECHNOLOGY INC
  • US8638612B2 patent drawing
  • US8638612B2 patent drawing
  • US8638612B2 patent drawing

AI summary

Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.