Asymmetric Active Fin Structures for Multi-Gate Transistors
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Solution Overview
Problem
The challenge in semiconductor devices is to enhance the operating performance and scalability of multi-gate transistors in highly-scaled integrated circuits while minimizing short channel effects and improving current controllability.
Innovation Solution
The semiconductor device incorporates active fin units with symmetric and asymmetric profiles on a semiconductor substrate, surrounded by device isolation layers, to optimize transistor structure and manufacturing processes, including the formation of sacrificial layers, spacers, and insulating layers to define and protrude active fins, ensuring precise control over fin profiles and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used with 3D channel structure, then current controllability and density are improved, but short channel effects become more significant
Solution Approach 1:
The patent applies asymmetry by configuring different numbers of active fins on opposite sides of the gate structure. Specifically, a first number of active fins are formed on a first side of the gate, while a second number of active fins are formed on a second side of the gate, where the first number differs from the second number. This asymmetric fin configuration allows optimization of current controllability while balancing the electrical characteristics to mitigate short channel effects.
2Productivity
If gate length is increased to improve current controllability, then operating performance improves, but device area increases
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional multi-gate structures with vertical active fins. The active fins extend vertically from the substrate, creating a 3D channel that provides enhanced gate control without increasing the lateral footprint of the device. This dimensional change allows improved operating performance while maintaining compact device area.
3Ease of manufacture
If symmetric active fin structures are used, then manufacturing simplicity is maintained, but current controllability is limited
Solution Approach 1:
The patent deliberately introduces asymmetry in the active fin configuration, with different numbers of fins on opposite sides of the gate. This asymmetric design provides superior current controllability compared to symmetric structures, while the fins are still formed using standard semiconductor manufacturing processes including sacrificial layer formation, spacer deposition, and selective etching.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are disclosed, which may improve the operating performance of a multi-gate transistor in a highly scaled integrated circuit device. The semiconductor device includes a first active fin unit protruding on a first region of a semiconductor substrate and extending along a first direction. The first active fin unit includes at least one first active fin having left and right profiles, which are symmetric to each other about a first center line perpendicular to a top surface of the semiconductor substrate on a cut surface perpendicular to the first direction. A second active fin unit protrudes on a second region of the semiconductor substrate and includes two second active fins, each having a left and right profiles, which are asymmetric to each other about a second center line perpendicular to the top surface of the semiconductor substrate on a cut surface.