Transistor TRIZ Cases

A control circuit adjusts the body potential of a MOSFET to turn off the device and isolate the integrated circuit from reverse power connections.

An aslant arrangement of photo diode and storage diode areas within a single unit pixel optimizes space utilization and enables global shutter functionality within the available pixel area, improving integration density.

A ray detector array substrate retains photoelectric conversion material inside via holes to prevent over-etching damage to underlying transistors.

Hydrogen plasma processing segregates silicon atoms to form an ultrathin protective layer on exposed silicon germanium surfaces.

A stressing layer enables boron doping implant to achieve high surface dopant concentration in semiconductor devices.

A light-absorbing layer contacts copper signal lines on a thin film transistor array substrate to minimize external light reflection.

Lateral bipolar transistors integrate into SOI structures to provide electrostatic discharge protection without additional masks.

Segmenting power handling into parallel switches reduces electrical losses and heat generation in fieldbus modules.

Dynamic gas flow rates in multi-step etching control liner and isolation feature heights to prevent fin bending caused by uneven stress distribution.

A conformal spacer mold self-aligns backside contacts to epitaxial source regions, relaxing lithography overlay constraints and reducing device area loss.

Alternating n-type and p-type regions in the peripheral section relax surface electric fields, raising avalanche voltage to improve withstanding capability.

A CMOS image sensor transfer transistor uses a buried channel region to move photo-generated charges efficiently.

Vertically stacked semiconductor wires surrounded by a gate structure reduce area occupation while enabling individual threshold voltage adjustment.

A current sensing circuit uses a sensing loop to maintain channel resistance and generate proportional output currents.

A protective metal layer shields transparent conductive pads in fringe field switching displays from etchant damage during patterning.

Trench contacts bridge thin and base substrate regions through the insulating layer, reducing footprint by eliminating surface metal connections.

A spacer structure defines contact hole dimensions to reduce data line linewidths, resolving manufacturing precision limits in high-resolution displays.

A strained silicon germanium fin structure maintains tensile strain in nFET regions while introducing compressive strain in pFET regions.

Segmented resistive elements increase total resistance without straddling the source region, reducing power consumption while maintaining stable current flow.

A high voltage semiconductor device uses a stepped drift region and gate electrode to shorten the current path.

Conforming a non-uniform depth profile drift region to trench isolation structures reduces implant energy and minimizes leakage current in integrated circuits.

Dielectric elements with lower refractive indices redistribute near-infrared light to boost quantum efficiency without increasing semiconductor thickness.

Nitride barrier layers prevent copper diffusion into oxide semiconductors while minimizing wiring resistance for stable display operation.

A light-emitting device integrates connecting and element continuity portions with the power supply line layer to simplify manufacturing steps.

A semiconductor device routes metal layer signals directly under a metal pad using an oxide insulation layer between the conductive layers.

Self-aligned isolation regions form via metal mask windows and contact openings, eliminating dedicated masks to lower manufacturing costs.

A dislocation-blocking mask directs threading dislocations to terminate at its sidewall during epitaxial growth.

Merging touch lines and light-shielding blocks into one metal layer reduces photomask usage, lowering production costs while improving process reliability.

Using gate metal electrodes and high-k dielectrics to fabricate MIM capacitors, reducing BEOL process steps and manufacturing costs.

An organic insulating layer blocks hydrogen diffusion to stabilize TFT characteristics during a-Si photo diode fabrication.

Selective etching forms air gaps in a fin structure stack, reducing parasitic capacitance and controlling short channel effects during device scaling.

High selectivity HBr and oxygen etching creates floating gate protrusions that concentrate the electric field, reducing erase voltage by 0.9 to 1.3 volts.

A voltage divider circuit feeds a temperature compensation block to stabilize trigger thresholds for electrostatic discharge protection.

Oxygen plasma converts a metal layer into a transparent insulating oxide, preventing etching damage to the IGZO active layer.

Deep trenched floating gates isolate drain and source regions to prevent leakage current while maintaining high breakdown voltage.

Selective etching removes implantation damage from silicon carbide devices, restoring minority carrier lifetime and enabling effective conductivity modulation.

Dual read sequences with distinct off voltages determine true data values in 3D NAND flash memory cells.

A doped back-plate structure dynamically biases pass gate transistors in SRAM bitcells to improve operational stability.

Transition metal nitride gate electrodes eliminate gate depletion and non-ideal effective work function in advanced CMOS devices.

Asymmetric active fin configurations mitigate short channel effects while enhancing current controllability in scaled integrated circuits.

FinFET transistors extract dummy gate stacks to resolve patterning difficulties while increasing drive currents without expanding chip area.

Protruding second contacts and trench silicide structures increase integration density while reducing layout design complexity in semiconductor fabrication.

Linear parallel layout structures optimize constructive light interference to resolve lithographic gap challenges in semiconductor manufacturing.

A semiconductor device uses segmented fin patterns and deep trench isolation to align gate structures across distinct regions.

A super source follower circuit clamps gate voltage to protect high-side switches from overvoltage damage.

Selective oxidation of an aluminum phosphide layer creates a reliable gate dielectric for complementary FETs on group III-V substrates.

A radiofrequency inductor uses a shielding structure covered by a mask pattern to reduce coupling capacitance.

Offset contact plugs overlap dielectric layers to lower parasitic resistance, aligning predicted and actual gate resistance for improved operation speed.

An intermediary control circuit connected between the gate and source of a SiC MISFET prevents erroneous turning-on caused by drain voltage changes.