Complementary FETs on Group III-V Substrate Using Selective Oxidation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in developing complementary Field Effect Transistors (FETs) on a common group III-V substrate, particularly in achieving similar performance and geometry for enhancement-mode (e-mode) and depletion-mode (d-mode) MOSFETs, as the difference in electron and hole mobility in these materials systems complicates device layout and manufacturing, and forming an effective gate dielectric for MOSFETs in group III-V material systems is difficult due to high interface traps and impurity absorption.
Innovation Solution
The solution involves forming enhancement-mode MOSFETs with a gate structure separated from the transistor body by a gate oxide, which is created by oxidizing an oxidizable material layer containing Aluminum and Phosphorus, while the depletion-mode FETs share a common substrate, either as MOSFETs, MESFETs, or HEMTs, with a Schottky layer, using the same oxidizable material layer for gate oxides and Schottky layers, ensuring no Arsenic is present, and selectively oxidizing portions to maintain desired device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complementary FETs are built on group III-V substrates, then device performance is improved, but the difference in electron and hole mobility requires disparate device sizing and geometry
Solution Approach 1:
The patent applies local quality by creating different device geometries in different regions of the substrate. N-channel devices utilize the high electron mobility material regions, while P-channel devices are designed with adjusted geometries to compensate for lower hole mobility. This allows each device type to be optimized locally for its carrier type while maintaining compatibility on the same substrate.
Solution Approach 2:
The patent changes physical parameters including device dimensions, gate lengths, and channel widths to compensate for mobility differences. By adjusting these geometric parameters, the patent achieves comparable performance between N-channel and P-channel devices despite the inherent mobility asymmetry in group III-V materials.
2Adaptability or versatility
If gate dielectric is formed in group III-V material systems, then MOSFET operation is enabled, but high interface traps and impurity absorption occur
Solution Approach 1:
The patent introduces an intermediary layer between the group III-V semiconductor and the gate dielectric. This intermediate buffer layer serves as a mediator that reduces interface trap formation and prevents impurity absorption at the dielectric-semiconductor interface, enabling reliable MOSFET operation on group III-V substrates.
Solution Approach 2:
The patent employs composite material structures consisting of multiple layers with different properties. The gate dielectric stack includes the primary dielectric layer combined with buffer and interface control layers, creating a composite structure that mitigates the harmful effects of direct contact between the gate dielectric and group III-V material.
3Area of stationary object
If e-mode and d-mode FETs are integrated on a single wafer, then component size is reduced, but manufacturing difficulty increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages that separately address e-mode and d-mode device formation. By dividing the manufacturing workflow into modular segments, the patent enables independent optimization of each device type while maintaining compatibility for integration on a single wafer.
Solution Approach 2:
The patent develops a universal fabrication platform that can produce both e-mode and d-mode FETs using common process steps and material layers. This multi-functional approach allows a single wafer to yield complementary device types through selective processing, reducing overall component footprint while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient and effective fabrication of complementary FETs on a common group III-V substrate, ensuring similar performance without disparate sizing, improving manufacturing ease and overall performance by using a reliable gate dielectric and maintaining desired doping levels for e-mode and d-mode operations.
Implementation Method 1
The gate oxide is preferably formed by oxidizing at least a portion of an oxidizable material layer that includes both Aluminum and Phosphorus
Data Source
AI summary
The present invention relates to providing an enhancement-mode (e-mode) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with a complementary depletion-mode (d-mode) FET on a common group III-V substrate. The depletion mode FET may be another MOSFET, a MEtal-Semiconductor FET (MESFET), a High Electron Mobility Transistor (HEMT), or like FET structure. In particular, the e-mode MOSFET includes a gate structure that resides between source and drain structures on a transistor body. The gate structure includes a gate contact that is separated from the transistor body by a gate oxide. The gate oxide is an oxidized material that includes Indium and Phosphorus. The gate oxide is formed beneath the gate contact.