Backside Contact Self-Alignment via Spacer Mold in GAA ICs
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Solution Overview
Problem
Conventional methods for fabricating gate-all-around integrated circuit structures face challenges in achieving precise alignment of backside contacts to epitaxial source or drain regions, leading to potential shorting issues and area loss due to non-self-aligned lithography processes, which hinder scaling and increase costs.
Innovation Solution
A processing scheme that utilizes a spacer mold to self-align the placement of an etch stop for backside contacts, allowing for absolute control of critical dimensions and overlay, and relaxes lithography overlay specifications, enabling tighter spacing between source and drain structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used for patterning, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to inability to achieve precise alignment of backside contacts to epitaxial source or drain regions
Solution Approach 1:
The patent applies preliminary action by forming the spacer mold structure before the actual contact patterning step. The spacer is deposited conformally on the gate structure, then selectively removed to create a mold that defines the contact position. This preliminary mold formation enables subsequent self-aligned etching, achieving precise alignment without requiring high-precision lithography overlay between separate patterning steps.
Solution Approach 2:
The spacer mold acts as an intermediary element between the gate structure and the backside contact. This intermediate structure transfers the gate position information to the contact formation process, enabling self-alignment. The spacer mold mediates the alignment relationship, allowing the contact to be precisely positioned relative to the epitaxial source or drain region through the intermediary mold structure rather than direct lithographic alignment.
2Area of stationary object
If non-self-aligned lithography processes are used, then device area can be reduced, but reliability deteriorates due to potential shorting issues from misalignment
Solution Approach 1:
The patent implements self-service through self-aligned contact formation where the spacer mold automatically defines the contact position relative to the gate structure. The etch process uses the spacer mold as a self-generated mask, eliminating the need for separate alignment procedures. This self-aligned approach ensures that contacts are precisely positioned to avoid shorting while minimizing device area, as the contact size and position are determined by the spacer dimensions rather than lithographic constraints.
3Productivity
If tighter spacing between source and drain structures is implemented, then productivity increases through higher density, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-aligned formation. By depositing spacers in the vertical dimension and using them as molds for lateral contact definition, the process achieves precise lateral positioning without relying on lithographic overlay precision. This dimensional transition enables tighter source-drain spacing because the critical lateral dimensions are controlled by conformal deposition thickness rather than lithographic resolution, relaxing overlay specifications while increasing integration density.
Data Source
AI summary
Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures.