SRAM Bitcell Back-Plate Biasing for Low-Voltage Operation
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Solution Overview
Problem
Static random access memory (SRAM) bitcells fabricated on a silicon-on-insulator (SOI) substrate face challenges in achieving improved minimum operating voltage (Vmin) and yield, as they struggle with power consumption, data retention, and read/write failures due to the limitations of pass gate transistors and pull-up/pull-down transistor ratios.
Innovation Solution
The SRAM bitcell structures incorporate a deep n-well layer, p-well regions, doped back-plate regions, and buried oxide layers, with shallow trench isolation and polysilicon gate conductors to dynamically bias pass gate transistors, allowing for improved voltage operation and yield by tuning the threshold voltage of transistors through contact to back-plate regions during read, write, or standby operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pass gate transistors are used to control access to SRAM bitcell, then read and write operations can be controlled, but the minimum operating voltage increases and yield decreases due to limitations in transistor ratio control
Solution Approach 1:
The patent introduces a back-plate structure beneath the pass gate transistors, adding a vertical dimension for bias control. By applying voltages to the back-plate through contacts extending through the substrate, the threshold voltage of pass gate transistors can be dynamically adjusted without changing the planar transistor geometry or ratios, thus improving yield while maintaining operational control.
Solution Approach 2:
The patent dynamically changes the threshold voltage parameter of pass gate transistors by applying different voltages to the back-plate during read, write, and standby operations. This parameter adjustment allows optimization of transistor performance and bitcell yield without requiring precise control of transistor dimensions or ratios during fabrication.
2Use of energy by moving object
If power supply voltage is reduced to lower power consumption, then energy efficiency improves, but the bitcell may fail to operate successfully below Vmin
Solution Approach 1:
The patent dynamically adjusts the threshold voltage of pass gate transistors by changing the back-plate bias voltage. During low-voltage operation, the back-plate voltage is adjusted to optimize the effective voltage swing across the bitcell, enabling successful read and write operations at supply voltages below the conventional Vmin while maintaining reliability.
Solution Approach 2:
The patent introduces dynamic control of pass gate transistor characteristics through time-varying back-plate biasing. The bias voltage is adjusted during different operational phases (read, write, standby) to optimize performance at each stage, allowing the bitcell to operate reliably across a wider voltage range including below traditional Vmin.
3Ease of operation
If deeper BP regions are used to improve transistor bias control, then threshold voltage tuning improves, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent uses shallow trench isolation regions that extend partially through the substrate to reach the back-plate, rather than requiring fully through-silicon vias or extremely deep trenches. This partial penetration approach provides sufficient electrical access to the back-plate for bias control while significantly reducing manufacturing complexity compared to complete substrate traversal.
Solution Approach 2:
The patent introduces shallow trench isolation regions as intermediary structures that facilitate electrical connection to the back-plate. These STI regions act as mediators, providing a practical manufacturing pathway to reach the back-plate without requiring excessively deep processing steps, thus balancing tuning capability with ease of manufacture.
Data Source
AI summary
Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pass gate (PG1) transistor and a second pass gate (PG2) transistor. The at least one CBP facilitates biasing of at least one the PG1 and PG2 transistors during at least one of a read, write or standby operation of the structures.