3D NAND Flash Memory Read Voltage Control for Threshold Saturation
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Solution Overview
Problem
Current three-dimensional NAND flash memory devices face challenges in achieving improved read characteristics, particularly due to saturation of threshold voltage with increasing electron density in charge storage regions, leading to difficulties in effectively utilizing high threshold voltage regions and potential issues with leakage currents.
Innovation Solution
The semiconductor memory device employs a multi-level memory structure with a p-type semiconductor region at one end of a memory string, utilizing a semiconductor layer with lower impurity concentrations and charge storage regions between conductive layers, along with a voltage control circuit to execute distinct read sequences with different off and read voltages, allowing for comparison and determination of true data values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a p-type semiconductor region is provided at one end of a memory string to achieve positive feedback, then read characteristic is improved, but threshold voltage saturation occurs with increasing electron density
Solution Approach 1:
The patent introduces a dual read sequence with different off voltages (first off voltage and second off voltage) to change the operational parameters of the memory device. By varying the off voltage applied to the p-type semiconductor region during read operations, the device can access different threshold voltage ranges, preventing saturation effects and enabling accurate reading of multi-level memory states.
Solution Approach 2:
The patent employs periodic alternating read sequences where the first read sequence and second read sequence are alternately executed. This periodic action allows the system to sample memory cell states under different voltage conditions, compare results, and determine true data values, thereby overcoming threshold voltage saturation issues.
2Quantity of substance
If multi-level memory structure is used to increase storage capacity, then data density is improved, but leakage current issues arise
Solution Approach 1:
The patent implements a feedback mechanism where read data from the first read sequence is compared with read data from the second read sequence. This comparison allows the system to identify and correct errors caused by leakage currents, ensuring accurate data retrieval from multi-level memory cells while maintaining data integrity despite the presence of harmful leakage effects.
Solution Approach 2:
The patent applies beforehand cushioning by executing read sequences with different off voltages before final data determination. This preliminary sampling under varied conditions cushions against the effects of leakage current, allowing the system to identify true data values even when leakage is present during individual read operations.
3Adaptability or versatility
If distinct read sequences with different off voltages are executed, then readable threshold voltage range is widened, but operation complexity increases
Solution Approach 1:
The patent merges multiple read operations into a unified dual read sequence framework. By combining the first read sequence and second read sequence with different off voltages into a single operational protocol, the system achieves widened threshold voltage readability while managing complexity through structured integration rather than separate independent operations.
Solution Approach 2:
The patent employs self-service through automatic comparison and determination logic that selectively identifies true read values from the two read sequences. The system automatically compares results from different off voltage conditions and determines authentic data without requiring external intervention, thereby managing operational complexity through automated decision-making processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the read characteristic of three-dimensional NAND flash memory by widening the range of readable threshold voltages, improving data reading accuracy and utilization of multi-level memory capabilities.
Implementation Method 1
a semiconductor layer that extends through the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, is between the n-type semiconductor region and the p-type semiconductor region, and has an n-type impurity concentration lower than an n-type impurity concentration of the n-type semiconductor region and a p-type impurity concentration lower than a p-type impurity concentration of the p-type semiconductor region
Data Source
AI summary
A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.