Polysilicon Floating Gate Protrusions for Faster Flash Memory Erasure
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Solution Overview
Problem
Traditional methods for forming split gate flash memory cells do not effectively create protrusions on the floating gate, which are necessary to increase the speed of Fowler-Nordheim tunneling for faster erasure and reduce power consumption, as they use low selectivity etch recipes that dull the surface and prevent protrusion formation.
Innovation Solution
A high selectivity etch recipe comprising hydrogen bromide (HBr) and oxygen is used to form recesses in the polysilicon floating gate layer, exposing protrusions that concentrate the electric field and enhance tunneling speed, allowing for faster erasure with lower voltage and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If low selectivity etch recipes are used to form the floating gate, then the etching process is easier to control, but the floating gate surface becomes dull and protrusions are prevented from forming
Solution Approach 1:
The etching process is divided into two distinct stages: a first etching step that forms the floating gate with adequate control, and a second etching step that specifically creates protrusions on the floating gate surface. This segmentation allows each step to be optimized independently - the first step ensures process control while the second step achieves the required surface precision for protrusion formation.
Solution Approach 2:
The first etching step performs a preliminary formation of the floating gate structure, creating a base surface that is then further processed. By performing this preliminary action with a controlled etch, the subsequent second etching step can focus specifically on creating protrusions without worrying about overall structure formation, thereby achieving both ease of manufacture and surface precision.
2Device complexity
If traditional etching methods are used, then the manufacturing process is simpler, but the Fowler-Nordheim tunneling speed is slower and power consumption is higher
Solution Approach 1:
The manufacturing process is segmented into multiple etching steps with different selectivity requirements. The first step uses low selectivity for general formation, while the second step uses high selectivity for protrusion creation. This segmentation increases manufacturing complexity but enables the floating gate surface geometry needed for faster Fowler-Nordheim tunneling, thereby improving erase operation speed.
Solution Approach 2:
The etching process parameters are changed between two steps: the first step uses parameters optimized for general etching control, while the second step uses parameters optimized for creating protrusions. This parameter change enables the floating gate to have the specific surface characteristics required for high-speed tunneling operations, trading some manufacturing complexity for improved productivity.
3Device complexity
If protrusions are not formed on the floating gate, then the manufacturing process is simpler, but the erase voltage requirement is higher and power consumption increases
Solution Approach 1:
The floating gate is preliminarily formed with a specific surface geometry through the two-step etching process, creating protrusions before the final device assembly. This preliminary action of shaping the floating gate surface reduces the energy required during subsequent erase operations by concentrating the electric field, thereby reducing power consumption while maintaining a relatively simple overall device structure.
Solution Approach 2:
The floating gate structure parameters are changed by creating surface protrusions through controlled etching. This parameter change in the floating gate geometry enables more efficient electric field distribution during erase operations, reducing the required erase voltage and power consumption without significantly increasing the overall device complexity.
4Speed
If protrusions are formed on the floating gate, then the Fowler-Nordheim tunneling speed increases, but the etching process becomes more complex
Solution Approach 1:
The complex task of forming protrusions is segmented into a two-step etching process. The first step handles the basic floating gate formation with controlled etching, while the second step specifically creates the protrusions. This segmentation manages the complexity by breaking down the process into manageable stages, each with specific objectives, thereby achieving high tunneling speed through protrusion formation without overwhelming process complexity.
Solution Approach 2:
The floating gate structure is preliminarily prepared in the first etching step, creating a foundation that facilitates the subsequent protrusion formation. This preliminary action simplifies the overall process by pre-positioning the floating gate correctly, so that the second step only needs to create protrusions without worrying about other structural considerations, thus achieving high tunneling speed with manageable complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The formation of protrusions using a high selectivity etch recipe increases the speed of Fowler-Nordheim tunneling, enabling faster erase operations while reducing the required erase voltage by 0.9 to 1.3 volts, thus improving performance and efficiency.
Implementation Method 1
A high selectivity etch recipe comprising hydrogen bromide (HBr) and oxygen is used to form recesses in the polysilicon floating gate layer
Implementation Method 2
exposing protrusions that concentrate the electric field and enhance tunneling speed
Implementation Method 3
increase the speed of Fowler-Nordheim tunneling for faster erasure
Data Source
AI summary
A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.