Strained SiGe Fin Structure for pFET and nFET CMOS Devices
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Solution Overview
Problem
The challenge lies in enhancing the performance of complementary metal oxide semiconductor (CMOS) devices beyond traditional scaling limits, where tensile strain in nFET devices is beneficial but not suitable for pFET devices, and compressive strain is needed for pFET fins to improve FinFET performance.
Innovation Solution
A method is developed to maintain tensile strain in nFET device regions using a strained silicon-on-insulator substrate while forming compressively strained silicon germanium alloy (SiGe) fins in pFET device regions by forming a hard mask, recessing the strained silicon layer, depositing SiGe layers with varying germanium content, and patterning the fins to achieve the desired strain configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tensile strained silicon fins are used in nFET devices, then device performance is improved, but the same structure is not suitable for pFET devices
Solution Approach 1:
The patent applies different strain configurations to different regions: tensile strain is maintained in the nFET region while compressive strain is introduced in the pFET region. This is achieved by selectively forming SiGe layers in the pFET region and using a hard mask to protect the nFET region during the strain modification process, allowing each device type to have its optimal strain configuration.
Solution Approach 2:
The semiconductor structure is divided into distinct nFET and pFET regions with different strain characteristics. The hard mask segments the structure to allow independent treatment of each region, enabling tensile strain preservation in nFET and compressive strain implementation in pFET simultaneously within the same substrate.
2Reliability
If compressive strain is added to pFET fins, then drive current is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent combines multiple functions into a unified process flow: the hard mask formation simultaneously protects the nFET region and defines the pFET region for SiGe layer deposition. The SiGe layer formation process simultaneously introduces compressive strain in pFET and prepares the structure for subsequent fin formation, reducing the need for separate processing steps.
Solution Approach 2:
The hard mask acts as an intermediary element that enables the complex strain differentiation process. It temporarily protects the nFET region during SiGe deposition, allows selective strain modification in the pFET region, and is later removed without affecting the underlying strained structures, simplifying the overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the maintenance of tensile strain in nFETs and the introduction of compressive strain in pFETs, enhancing device performance by optimizing the semiconductor structure for improved drive currents and further scaling capabilities.
Implementation Method 1
A thermal condensation process is then performed to convert the strained silicon layer in the pFET device region into a second SiGe layer having the first Ge content and being relaxed.
Data Source
AI summary
A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.