FinFET LDD Extensions via Dummy Gate Extraction
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Solution Overview
Problem
The challenge is to enhance the drive currents of FinFET transistors while maintaining a compact chip area, as existing multi-fin FinFET designs face difficulties in patterning due to dummy gate stacks, which can interfere with the formation of adjacent FinFETs.
Innovation Solution
The method involves forming multiple semiconductor fins with a gate structure and source/drain regions, using epitaxial growth for source/drain extensions and spacers to increase carrier mobility, and strategically removing gate electrode and dielectric layers to optimize channel width and reduce short channel effects, while managing dummy gate stacks for better isolation between adjacent devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple fins are formed to increase channel width and drive current, then drive current increases, but chip area usage increases
Solution Approach 1:
The patent transitions from planar 2D transistor channels to three-dimensional FinFET structures with vertical fins extending from the substrate. By adding the vertical dimension, the channel width is effectively increased without proportionally increasing the horizontal chip area, as multiple fins can be packed more densely in the planar direction while providing three-dimensional current conduction paths.
2Ease of manufacture
If dummy gate stacks are used between FinFETs to aid processing, then manufacturing is facilitated, but patterning difficulty increases due to interference with surrounding fins
Solution Approach 1:
The patent removes the dummy gate stacks from between the FinFETs, extracting the problematic element that was causing patterning interference. Instead of using dummy structures to aid processing, the design relies on the actual FinFET structures themselves, eliminating the source of patterning difficulties while maintaining manufacturing feasibility through optimized fin geometry and spacing.
3Power
If channel width is maximized to increase drive current, then drive current increases, but short channel effects worsen
Solution Approach 1:
The FinFET structure utilizes vertical fins to increase effective channel width while maintaining short horizontal channel lengths. The three-dimensional configuration provides better gate control over the channel through wrap-around gates that contact the fin sidewalls, suppressing short channel effects even as drive current increases through multiple parallel fins.
Solution Approach 2:
The gate structure wraps around the fin channels in a nested configuration, with the gate electrode surrounding the channel region on multiple sides. This nested gate-channel arrangement enhances gate control and reduces short channel effects by providing electrostatic control from multiple directions, while still allowing maximized channel width through multiple fins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases drive currents without expanding chip area, improves carrier mobility, and reduces short channel effects by strategically forming and patterning gate and dielectric layers, and managing dummy gate stacks for better isolation between FinFETs.
Implementation Method 1
using epitaxial growth for source/drain extensions and spacers to increase carrier mobility
Data Source
AI summary
System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.