Metal Pad Routing Under Metal Layer for Semiconductor Layout Area Reduction
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Solution Overview
Problem
Conventional semiconductor devices require a large layout area due to the inability to form metal lines under metal pads, limiting their design efficiency.
Innovation Solution
The semiconductor device incorporates a first specific metal layer routing formed directly under a metal pad in a second metal layer, with an oxide layer between the metal layers, allowing for reduced layout area by optimizing metal pad placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If metal lines are not formed under metal pads in conventional semiconductor devices, then the manufacturing process is simpler, but the layout area becomes larger
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by forming metal layer routing directly under the metal pad in a lower metal layer. This vertical arrangement allows power and ground lines to be routed underneath the pad without occupying lateral space, thereby reducing the overall layout area while maintaining manufacturing feasibility through the oxide layer insulation structure.
2Area of stationary object
If metal layer routing is formed directly under metal pad, then the layout area is reduced, but the risk of electrical interference or short circuit increases
Solution Approach 1:
The patent introduces an oxide layer as an intermediary insulating structure positioned between the first metal layer (containing the metal pad) and the second metal layer (containing the routing). This oxide layer acts as a mediator that prevents direct electrical contact between adjacent metal layers, thereby eliminating short circuit risks while enabling the compact vertical routing configuration.
3Area of stationary object
If oxide layer is positioned between metal layers to enable routing under pad, then layout area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The oxide layer is formed as part of the interlayer dielectric structure during the standard semiconductor manufacturing process sequence. By incorporating the oxide layer formation into the preliminary manufacturing steps (as an interlayer dielectric), the structure is established before final routing patterning, ensuring proper positioning and alignment without requiring additional high-precision steps.
Data Source
AI summary
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.