Offset Contact Plug in Semiconductor Memory Gate Structure
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Solution Overview
Problem
In semiconductor devices, particularly non-volatile memory devices, increased gate resistance leads to operation speed decreases and potential malfunctions due to errors between predicted and actual gate resistance, affecting the integration and reliability of the devices.
Innovation Solution
The implementation of a semiconductor device structure with offset contact plugs that overlap a dielectric layer, reducing parasitic resistance and enhancing the reliability of the gate insulating layer by connecting gate patterns in parallel and using a stacked structure of conductive layers with a metal silicide layer to lower resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase degree of integration, then device density is improved, but gate resistance increases causing operation speed to decrease
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) connected in parallel, which reduces the gate resistance while maintaining the same transistor footprint. This segmentation allows current to flow through multiple parallel paths, effectively lowering the total resistance without requiring larger transistor dimensions.
Solution Approach 2:
The patent introduces an additional spatial dimension by stacking conductive layers vertically. The first conductive layer and second conductive layer are positioned at different heights, creating a three-dimensional structure that reduces parasitic resistance by providing multiple current paths in the vertical dimension while keeping the planar area unchanged.
2Quantity of substance
If transistor size is reduced to increase degree of integration, then device density is improved, but gate resistance error between predicted and actual values increases causing malfunction
Solution Approach 1:
Dividing the gate into multiple parallel-connected electrodes reduces the actual gate resistance to better match the predicted resistance values from transistor models. This segmentation ensures that the electrical characteristics remain predictable and reliable even as transistor dimensions are scaled down for higher integration.
Solution Approach 2:
The patent modifies the electrical parameters by introducing parallel conductive paths through multiple conductive layers and offset contact plugs. This changes the resistance characteristics to align better with theoretical predictions, improving reliability while maintaining miniaturization.
3Device complexity
If contact plug is positioned directly under gate pattern, then connection is simplified, but electric field stress on gate insulating layer increases causing malfunction
Solution Approach 1:
The contact plug is deliberately positioned asymmetrically relative to the gate pattern, creating an offset configuration. This asymmetric placement moves the contact plug away from the high-stress region directly under the gate, reducing electric field concentration on the gate insulating layer while still maintaining effective electrical connection through the dielectric layer.
Solution Approach 2:
The dielectric layer serves as an intermediary medium between the contact plug and the gate pattern. By positioning the contact plug to overlap the dielectric layer rather than being directly under the gate, the dielectric layer mediates the electric field distribution, reducing stress on the gate insulating layer while still providing the necessary electrical connection path.
Data Source
AI summary
The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.