Asymmetric Clock Frequency for Smart Card Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for programming data into electronic devices, such as smart cards and cellular phones, are inefficient due to the use of a single clock frequency for both transmitting and receiving data, which increases programming time and manufacturing costs as the amount of data stored in these devices grows.
Innovation Solution
A host component facilitates data transmission to electronic devices using a faster downlink clock speed than the uplink clock speed, allowing for asynchronous communication and reducing programming time by dynamically selecting the downlink clock frequency based on the electronic device's capabilities, while maintaining compatibility with standard protocols like ISO 7816-3.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single clock frequency is used for both transmitting and receiving data, then compatibility with standard protocols is maintained, but programming time increases and productivity decreases
Solution Approach 1:
The patent implements dynamic clock frequency selection where the electronic device can operate at different clock frequencies depending on the operation type. During downlink (programming), a higher clock frequency is used to increase data transfer speed, while during uplink (reading), a lower clock frequency is used to maintain compatibility with standard protocols. This dynamic adaptation resolves the contradiction between protocol compatibility and programming speed.
Solution Approach 2:
The patent changes the clock frequency parameter based on the direction of data transfer. By allowing the clock frequency to vary between downlink and uplink operations, the system achieves faster programming speeds during data writing while maintaining protocol compatibility during data reading, thus resolving the contradiction between productivity and adaptability.
2Loss of time
If a higher clock frequency is used for data transmission, then programming time is reduced, but device complexity increases
Solution Approach 1:
The patent segments the clock frequency management into separate handling for downlink and uplink operations. The host component is responsible for managing the higher clock frequency during downlink, while the electronic device manages the lower clock frequency during uplink. This segmentation distributes the complexity across different components rather than requiring the electronic device to handle both high-speed transmission and protocol compatibility alone.
Solution Approach 2:
The host component acts as an intermediary that manages the clock frequency transitions and coordinates between the higher speed requirements for downlink and the protocol requirements for uplink. This intermediary role simplifies the electronic device's burden by handling the complex frequency management externally.
3Productivity
If asymmetric clock frequencies are used for downlink and uplink, then data transfer efficiency is improved, but communication protocol compatibility is reduced
Solution Approach 1:
The patent applies different clock frequency qualities to different communication directions. The downlink uses higher clock frequency optimized for fast data writing, while the uplink uses lower clock frequency optimized for protocol compatibility. This local differentiation of communication parameters allows each direction to be optimized for its specific purpose without compromising the other.
Solution Approach 2:
The system dynamically switches between different clock frequency modes based on the operation type. During programming operations, the system transitions to higher clock frequencies for improved efficiency, while during reading operations, it transitions to lower clock frequencies for protocol compatibility. This dynamic behavior allows the system to adapt to different operational requirements.
Data Source
AI summary
Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the determination of different clock frequencies that an electronic device(s) can accommodate for transmitting data to and receiving data from the electronic device. The host component can facilitate transmitting data to the electronic device at a higher clock frequency than the clock frequency utilized to transmit data from the electronic device to the host component in order to facilitate programming large amounts of data to the electronic device efficiently. The host component can select a downlink and/or uplink clock frequency based in part on the type of electronic device(s), the size of a memory buffer associated with the nonvolatile memory device, and/or a type of protocol associated with the electronic device.