Generating/Distributing Signals TRIZ Cases
- Gating Circuit for Memory Timing Signal Filtering
A gating circuit filters timing signals by opening a window during the preamble portion to pass valid data regions.
- Asynchronous Finite State Machines with Fork Join Logic
Asynchronous finite state machines use fork and join logic to coordinate state transitions without a shared clock signal.
- Signal Acquisition Managing Device for Microcontroller Load Reduction
A signal acquisition managing device generates synchronized command signals to reduce computational load on a processor core.
- Dithered Pulse Phase Interpolation for Audio Clock Synthesis
Digital logic replaces complex PLLs and NCOs by using fractional phase accumulation to generate rational submultiples, reducing FPGA resource usage.
- Clock Generator Phase Synchronization for Dispersed Semiconductor Blocks
A clock generator synchronizes frequency-divided PLL clock phases across dispersed semiconductor data transfer blocks.
- Programmable Drive Strength in Memory Signaling Circuits
A signal modulator adjusts drive strength for memory output lines based on control inputs to optimize electrical characteristics.
- Asymmetric Clock Frequency for Smart Card Programming
Host component transmits data to electronic devices using a faster downlink clock speed than the uplink clock speed.
- Dynamic Optimization of Cryptocurrency Mining Processing Units
A control system dynamically adjusts voltage and frequency settings in processing units to optimize operational parameters.
- Shared Memory Bus Controller for SDRAM and Flash Pin Reduction
A shared memory bus controller manages simultaneous access to synchronous and asynchronous memories using common address and data terminals.
- One-Wire Bus Manchester Encoding for High-Speed RF Control
Manchester encoding embeds clock signals in data transmissions on a single wire, achieving 52 MHz rates while reducing GPIO pin counts.
- Glitch-Free Clock Domain Crossing via Synchronization Registers
A synchronization register attached to domain crossing logic prevents output signal transitions at selected clock cycle intervals.
- Clock Source Frequency Transition Control for Memory Stability
Calibrated frequency hopping preserves memory access availability while reducing power consumption.