External Clock Circuit for Microsecond Waiting Delay
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Solution Overview
Problem
Existing software-only solutions for waiting delays in microseconds are not precise, as they depend on compiler-specific optimizations, leading to inconsistent and often longer than necessary waiting times.
Innovation Solution
A timing method utilizing an external clock circuit with a counter configured to increment or decrement its value over a range of values corresponding to one millisecond, where the central processing unit monitors transitions of a designated bit to achieve a desired waiting delay independent of compiler variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a software loop is used to provide a waiting delay in microseconds, then the solution is simple and does not require additional hardware, but the precision of the waiting delay deteriorates due to compiler-specific optimizations
Solution Approach 1:
The patent introduces an intermediary hardware component (the dedicated clock circuit with counter) that mediates between the software waiting delay requirement and the precise timing need. This external clock circuit serves as a mediator that provides accurate timing without requiring complex software loops, resolving the contradiction by adding a simple hardware intermediary rather than complex software.
Solution Approach 2:
The patent replaces the software-based timing mechanism (which depends on compiler optimizations and CPU cycles) with a hardware-based clock circuit that uses dedicated clock strokes. This substitution of mechanical/software system with a more reliable hardware timing system eliminates the precision issues caused by compiler variations while maintaining simplicity.
2Device complexity
If a software loop is used to provide a waiting delay, then no additional hardware is required, but the waiting time increases due to added waiting margins to compensate for imprecision
Solution Approach 1:
The dedicated clock circuit acts as an intermediary that provides precise timing without requiring additional waiting margins. By using this intermediary hardware component, the system achieves accurate waiting delays without the need to add compensatory time, thereby reducing overall waiting time while maintaining simplicity.
Solution Approach 2:
The patent implements a feedback mechanism where the software loop monitors the hardware counter and uses this feedback to determine when to exit the waiting loop. This feedback from the hardware timing circuit to the software allows for precise timing without adding unnecessary waiting margins, resolving the contradiction between hardware simplicity and time efficiency.
3Measurement precision
If a dedicated clock circuit is used to count in microseconds, then timing precision is improved, but the device complexity increases due to additional hardware resources
Solution Approach 1:
The patent makes the dedicated clock circuit universal by configuring it to serve multiple purposes: it provides precise microsecond timing for waiting delays, and can also be used for other timing-related functions in the system. This multi-functionality justifies the added hardware complexity by providing versatile timing capabilities rather than a single dedicated function.
Solution Approach 2:
The patent changes the parameter of timing resolution from software-based (dependent on CPU frequency and compiler) to hardware-based (direct clock stroke counting). By changing the fundamental parameter of how timing is measured and controlled, the system achieves superior precision while the hardware complexity remains acceptable due to the straightforward implementation of the clock circuit.
4Productivity
If compiler optimizations are applied to reduce waiting time, then productivity is improved, but measurement precision deteriorates due to variations in instruction count
Solution Approach 1:
The dedicated clock circuit serves as an intermediary that decouples the software execution speed (productivity) from the timing precision requirement. The hardware counter independently tracks the precise number of clock strokes, allowing the software to be optimized for speed without affecting timing accuracy, thus resolving the contradiction between productivity and precision.
Solution Approach 2:
The patent replaces the software-based timing measurement (which is affected by compiler optimizations and instruction count variations) with a hardware-based counter that directly measures clock strokes. This substitution eliminates the dependency between compilation optimizations and timing precision, allowing maximum productivity through optimization while maintaining accurate timing measurement.
Data Source
AI summary
According to one aspect, provision is made of a timing method implemented by a computer system comprising: a central processing unit, an external clock circuit comprising a counter, the counter being configured to increment or decrement its value with each clock stroke of the external clock circuit over a range of values corresponding to one millisecond, the timing method comprising: defining a maximum number of transitions of a bit to be monitored of the counter value corresponding to a desired waiting delay, monitoring transitions of the bit to be monitored of the counter value so as to achieve the timing until the number of performed transitions of the bit to be monitored reaches the defined maximum number of transitions.