Multi-Clock Buffer Skew Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic chip design, using multiple clocking signals generated from a common clock source leads to increased power consumption and significant clock skew and jitter due to process, voltage, and temperature variations, especially in programmable applications where requirements are not known in advance.
Innovation Solution
The synthesis of Hardware Description Language (HDL) code generates a netlist that places and routes multi-clock buffers to produce the least divided clocking signal locally near loads, reducing the need for multiple clock signals to be fanned out across the chip, thereby minimizing power usage and clock skew by ensuring all clock signals are subject to the same PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clocking signals are distributed throughout the chip from a common clock source, then clocking requirements for different loads are met, but power consumption increases and clock skew and jitter occur due to PVT variations
Solution Approach 1:
The patent segments the clock distribution into two parts: a single shared clock signal is distributed from the clock source to a multi-clock buffer, while individual clocking signals are generated locally at each load region. This segmentation reduces the number of long-distance clock signal routes, thereby reducing power consumption while still meeting diverse clocking requirements of different loads
Solution Approach 2:
The patent implements local quality by placing multi-clock buffers and clock modifying leaves close to the loads. These local components generate clock signals with specific characteristics (division ratios, phases) tailored to the needs of nearby loads, reducing the need to distribute multiple different clock signals across the entire chip and thus reducing overall power consumption
2Adaptability or versatility
If multiple clocking signals are routed throughout the chip, then different loads receive appropriate clock signals, but clock skew and jitter increase due to process, voltage, and temperature variations
Solution Approach 1:
The patent segments the clock path so that a single shared clock signal travels from the source to the multi-clock buffer, and then individual clock signals are generated locally at each load. This segmentation ensures that all loads derive their clock signals from the same original clock edge through local division, eliminating skew caused by different signal paths experiencing different PVT variations
Solution Approach 2:
The multi-clock buffer acts as an intermediary component that receives a single clock signal and generates multiple divided clock signals locally. By placing this intermediary close to the loads, the patent ensures that all clock signals are generated from the same source timing reference, reducing clock skew and jitter while still providing the adaptability needed for different clocking requirements
3Adaptability or versatility
If multiple clocking signals are fanned out across the chip, then all loads receive clock signals, but the complexity of clock routing and synchronization increases
Solution Approach 1:
The patent makes the shared clock signal universal by using it to drive a multi-clock buffer that generates all necessary divided clock signals. This single shared clock path serves multiple functions: it provides the timing reference for all loads and enables local generation of various clock division ratios, thereby reducing routing complexity while maintaining comprehensive clock signal coverage
Solution Approach 2:
The patent implements self-service by enabling each load region to generate its own specific clock signals locally using multi-clock buffers and clock modifying leaves. This eliminates the need for complex centralized routing of multiple different clock signals across the chip, as each region independently generates its required clock signals from the shared clock source
Data Source
AI summary
Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.