Asynchronous Bridge Circuitry for Low-Overhead Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As data processing speeds increase, controlling data transfer across asynchronous clock domains becomes challenging due to growing time delays, and existing asynchronous bridge circuitry incurs high overhead, particularly in managing the first-in-first-out buffer and synchronizing data across clock domain boundaries.
Innovation Solution
The proposed asynchronous bridge circuitry includes a first-in-first-out buffer within the source clock domain, transmission path circuitry, write pointer circuitry, and transmission control circuitry with tracking values to manage data transfer efficiently, decoupling the write pointer and transmission control from the destination end to prevent data overflow and ensure proper synchronization without incurring additional delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the first-in-first-out buffer is located within the source clock domain close to the destination circuitry, then wiring overhead is reduced, but control of data transfer becomes more difficult due to transmission delays
Solution Approach 1:
The system segments the control function by separating the write pointer circuitry (located near the buffer in the destination clock domain) from the transmission control circuitry (located near the source in the source clock domain). This segmentation allows each component to operate independently in its own clock domain, reducing the complexity of cross-clock-domain control while maintaining low wiring overhead through the localized buffer placement.
2Productivity
If data processing speed increases, then processing capability is improved, but controlling data transfer across clock domains becomes more difficult due to growing time delays
Solution Approach 1:
The system implements feedback through tracking circuitry that monitors the state of the first-in-first-out buffer (such as full/empty conditions) and uses this information to control data transmission. This feedback mechanism allows the transmission control circuitry to dynamically adjust data flow based on buffer status, ensuring reliable operation even as transmission delays increase with higher processing speeds.
Solution Approach 2:
The write pointer circuitry preliminarily determines the write location in the buffer before data arrives, and the transmission control circuitry preliminarily controls whether data should be sent based on tracked buffer state. This preliminary action prevents overflow or underflow conditions before they occur, enabling the system to handle high-speed data transfer reliably despite increasing transmission delays.
3Ease of operation
If transmission control circuitry is located remotely from the first-in-first-out buffer, then control of source circuitry is improved without transmission delay, but tracking of buffer state becomes more complex
Solution Approach 1:
The tracking circuitry maintains simplified copies of the buffer state (such as full/empty status bits) rather than complete replicas of all buffer contents. This copying approach allows the remotely located transmission control circuitry to effectively monitor and control data flow based on essential buffer state information, reducing the complexity of remote tracking while maintaining effective control.
Data Source
AI summary
Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data. The transmission control circuitry includes tracking circuitry which stores one or more tracking values for tracking respective state variables of the first-in-first-out buffer and controlling whether or not the transmission control circuitry permits the sending of data from the source to the destination in dependence upon the generated control circuitry.