Centroid Clock Synchronization for Computational Systems
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Solution Overview
Problem
Existing clock synchronization algorithms for processing devices, such as leader/follower and second edge techniques, face challenges like synchronization issues, drift problems, and confusion when units power on or drop out, leading to inefficiencies and resource burdens in achieving uniform clock synchronization across asynchronous systems.
Innovation Solution
The centroid synchronization algorithm determines the phase centroid of a cluster of pulses from multiple clock sources, adjusting each local clock to align with the majority, using hysteresis and analysis windows to prevent oscillations and ensure seamless addition or removal of computational units, thus synchronizing clocks efficiently and uniformly without the need for designating leaders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If leader/follower synchronization approach is used, then a designated leader pulse can guide synchronization, but synchronization issues occur when multiple units declare themselves as leader simultaneously
Solution Approach 1:
The patent extracts the leader selection problem from the synchronization algorithm by using an external reference clock source. Instead of having units internally determine leadership through complex algorithms, the reference clock externally provides the synchronization signal, eliminating the need for leader election logic and preventing conflicts when multiple units claim leadership.
Solution Approach 2:
The reference clock acts as an intermediary between the asynchronous units. Rather than units directly synchronizing with each other through complex peer-to-peer algorithms, the reference clock mediates the synchronization process by providing a common time reference that all units can independently align to, simplifying the overall system complexity.
2Reliability
If leader/follower synchronization is implemented, then clock synchronization can be achieved, but drift issues arise when the designated leader has pronounced local clock drift
Solution Approach 1:
The patent extracts the clock reference function from the potentially drifting unit clocks and places it in an external reference clock source. By taking out the reference function from the unreliable local oscillators, the system avoids inheriting their drift characteristics while maintaining synchronization capability.
Solution Approach 2:
The system creates copies of the reference clock signal and distributes them to all units. Each unit receives an identical copy of the reference clock, ensuring they all synchronize to the same accurate time base rather than each unit potentially drifting from its own local oscillator characteristics.
3Reliability
If second edge technique is used, then units can synchronize to the second leading edge pulse, but confusion occurs when more than one unit is selected as second edge during power on
Solution Approach 1:
The reference clock serves as an intermediary that eliminates the need for units to perform complex second-edge detection algorithms. Instead of units independently identifying and synchronizing to the second leading edge through sophisticated detection logic, the reference clock directly provides the synchronization signal, removing the algorithmic complexity while maintaining stability.
4Reliability
If traditional synchronization algorithms are implemented, then clock alignment can be achieved, but resource consumption increases due to the complexity of handling various edge cases
Solution Approach 1:
The patent extracts the complex decision-making logic from the processing units and places it in the external reference clock system. By taking out the algorithmic complexity of handling power-on sequences, drop-out conditions, and edge-case management from the computational units, the system reduces processing resource consumption while maintaining robustness through the simplified reference-based approach.
Data Source
AI summary
Provided for herein are systems, methods, apparatus and software configured synchronize clocks across two or more processing devices. The techniques of the present disclosure include: obtaining, at a processing device, indications of clocks, wherein the indications comprise an indication for a clock for each of a plurality of processing devices; determining, from the indications, whether a clock of the processing device leads or lags a majority of clocks of the plurality of processing devices; and adjusting the clock of the processing device in a direction of the majority of the clocks of the plurality of processing devices.