UART Sampling Signal Circuit with Dynamic Clock Division
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Solution Overview
Problem
Existing UART interfaces face challenges in generating a sampling signal with adjustable frequency that corresponds precisely to the bit rate, as simple division of the peripheral clock does not allow for arbitrary sampling signal frequencies.
Innovation Solution
A circuit that includes a bit rate memory, a peripheral clock memory, a sum memory, and a computing unit to generate a sampling signal by comparing a sum value with a threshold value, adjusting it based on the peripheral clock, and using a multiplexer to output the signal, allowing for precise adjustment of the sampling signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple division of the peripheral clock is used to generate the sampling signal, then the device complexity is reduced, but the manufacturing precision of the sampling signal frequency is insufficient and cannot achieve arbitrary bit rates
Solution Approach 1:
The patent changes the parameters of the peripheral clock by storing multiple different frequency values in a register (e.g., 50, 52, 54, ..., 100 MHz) and dynamically selecting appropriate division ratios. This allows the sampling signal frequency to be precisely adjusted to match arbitrary bit rates while maintaining a manageable circuit structure through parameter variation rather than structural complexity.
Solution Approach 2:
The patent introduces dynamic adjustability to the clock division process by allowing the division ratio to be changed based on the selected peripheral clock frequency and desired bit rate. The system dynamically selects from multiple stored frequency values and adjusts the division ratio accordingly, enabling precise frequency matching for different communication standards without requiring a fixed complex circuit.
2Manufacturing precision
If multiple different peripheral clock frequencies are stored and compared to achieve precise sampling signal frequency, then the sampling signal frequency precision is improved, but the device complexity increases due to additional memory and computing units
Solution Approach 1:
The patent segments the frequency selection process into distinct functional modules: a register storing multiple peripheral clock frequency values, a separate computing unit for comparison and calculation, and a control logic for selecting the appropriate division ratio. This segmentation allows each component to perform its specific function efficiently, achieving precise frequency matching while keeping the overall circuit structure organized and manageable.
Solution Approach 2:
The patent introduces an intermediary computing unit that acts as a mediator between the stored peripheral clock frequencies and the sampling signal generation. This computing unit compares the stored frequencies with the desired bit rate, calculates the appropriate division ratio, and controls the frequency selection process, thereby achieving precise frequency control without requiring direct complex interconnections between all components.
Data Source
AI summary
A circuit for generating a sampling signal for a UART interface has an input terminal designed to receive a peripheral clock, an output terminal designed to output the sampling signal, a bit rate memory designed to store a value corresponding to a desired bit rate of the UART interface, a peripheral clock memory designed to store a value corresponding to a frequency of the peripheral clock, a sum memory designed to store a sum value, and a computing unit. The computing unit compares a comparison value, which is dependent on the sum value stored in the sum memory, with a threshold value, which is dependent on the value stored in the peripheral clock memory. The result of the comparison is taken as a basis for generating the sampling signal at a first level or a second level. In step with the peripheral clock and on the basis of the result of the comparing, the sum value stored in the sum memory is altered by the value stored in the bit rate memory or the sum value stored in the sum memory is altered by a value that is dependent on the value stored in the peripheral clock memory.