Latency Control Circuit Power Reduction via Periodic Clock Shifting
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Solution Overview
Problem
Existing latency control circuits in semiconductor memory devices consume excessive power due to continuous clock signal toggling, which is not optimized for efficient shifting operations.
Innovation Solution
A latency control circuit design that includes clock synchronization units shifting an input signal only at the time of input, with a clock supply block allocating clock signals based on control signals, and a selection output block selecting signals based on latency information, minimizing power consumption by toggling clock signals only during shifting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signals are continuously toggled in existing latency control circuits, then the shifting operation can be performed, but power consumption increases excessively
Solution Approach 1:
The patent applies periodic action by enabling clock signals only during specific periods when shifting operations are actually needed. The control circuit generates enable signals that activate clock signals in a periodic manner corresponding to the latency periods, rather than continuously toggling them. This ensures clock synchronization units perform shifting operations only when necessary, minimizing power consumption while maintaining productivity.
2Use of energy by moving object
If clock signals are toggled only during shifting operations, then power consumption is minimized, but the timing coordination becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the clock supply function into multiple independent clock synchronization units, each with its own enable signal control. The clock supply block is segmented to provide clock signals to different units independently based on latency information. This segmentation allows precise control of clock toggling in each unit without requiring complex centralized coordination, thus minimizing power consumption while keeping the overall device complexity manageable.
3Adaptability or versatility
If multiple clock synchronization units are used to achieve desired latency, then latency flexibility is improved, but the number of units increases device complexity
Solution Approach 1:
The patent applies dynamics by making the activation of clock synchronization units dynamic based on latency information. Instead of having all units continuously active or fixed in configuration, the control circuit dynamically enables or disables specific units based on the required latency period. This dynamic control allows the system to achieve various latency values using a fixed number of units, improving latency flexibility without proportionally increasing device complexity.
Data Source
AI summary
A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal, and a clock supply block configured to sequentially supply the clock signals to the plurality of clock synchronization units.