SOC PLL Fault Detection and Alternate Clock Switching
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Solution Overview
Problem
Integrated circuit (IC) devices face functional safety risks due to faults in clocking elements that also affect monitoring and error-reporting functionality, leading to potential device failures in mission-critical systems.
Innovation Solution
Implementing a mechanism to detect clocking element faults and switch to an alternate clock, allowing error reporting to continue by using an alternate clocking element, such as a phase-locked loop (PLL), and sending error messages through Intellectual Property (IP) cores to a system-on-a-chip (SOC) via the SOC Functional Safety (FuSA) error reporting infrastructure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If monitoring and error-reporting circuitry uses the same clocking element as the IC device, then device complexity is reduced, but reliability deteriorates because a fault in the clocking element causes faults in both the device and monitoring circuitry
Solution Approach 1:
The patent divides the clocking system into separate functional segments: a primary clocking element for device operation and a secondary clocking element for monitoring and error-reporting circuitry. This segmentation isolates faults, allowing the monitoring circuitry to continue operating even if the primary clocking element fails, thereby improving functional safety without requiring complete system redundancy.
Solution Approach 2:
The patent introduces an intermediary clocking element (secondary clocking element) that serves as a dedicated timebase for the monitoring and error-reporting circuitry. This intermediary component ensures that the monitoring function has an independent time reference, preventing propagation of clocking faults to the monitoring system while maintaining overall system reliability.
2Reliability
If a fault in the clocking element is detected, then reliability is improved by switching to alternate clock, but loss of time occurs during the switching transition
Solution Approach 1:
The patent implements preliminary action by pre-configuring the monitoring and error-reporting circuitry with a secondary clocking element before any fault occurs. The error-reporting logic is prepared in advance to switch to the alternate clock immediately upon detecting a fault condition, minimizing the transition time and ensuring continuous operational awareness without significant time loss.
3Reliability
If error reporting continues using alternate clock, then reliability is improved, but device complexity increases due to additional clocking element and switching logic
Solution Approach 1:
The patent applies universality by designing the secondary clocking element to serve multiple functions: it provides the timebase for monitoring circuitry, enables error detection, supports error-reporting operations, and facilitates fault isolation. This multi-functional approach improves reliability through continued operation while minimizing the increase in device complexity by consolidating multiple functions into a single redundant component.
Data Source
AI summary
The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.