Signal Synchronizing Device for Mixed-Frequency Clock Domains
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Solution Overview
Problem
Conventional signal synchronizing devices for systems on a chip are limited in applicability and incur higher hardware costs when dealing with clock signals of different frequencies, requiring additional circuits for frequency conversion and ratio calculation.
Innovation Solution
A signal synchronizing device comprising a trigger module, a first storage unit, and a synchronizing module that generates a trigger signal and performs synchronous transfer between clock signals of different frequencies without the need for prior knowledge of frequency relationships, allowing operation in both asynchronous and synchronous modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the conventional signal synchronizing device is used, then the device can synchronize signals between two clock signals, but the device has limited applicability and requires additional circuits when the frequency relationship between clock signals is not known in advance
Solution Approach 1:
The patent implements a universal synchronizing device that can handle both asynchronous and synchronous clock signal frequency relationships using the same circuit structure. The device automatically adapts to different frequency conditions without requiring additional circuits or prior knowledge of frequency relationships, thereby achieving multi-functionality and eliminating the need for separate frequency conversion circuits.
Solution Approach 2:
The synchronizing device performs self-adjustment based on the automatic detection of clock signal frequency relationships. The device autonomously determines whether to operate in asynchronous or synchronous mode without external intervention or pre-configuration, enabling self-service operation that simplifies the system and reduces hardware complexity.
2Ease of operation
If the conventional signal synchronizing device is used, then the device can synchronize signals, but the device requires prior knowledge of which clock signal frequency is faster
Solution Approach 1:
The patent employs automatic frequency detection mechanisms where the device autonomously identifies the faster clock signal and adjusts its operation accordingly. This self-service approach eliminates the need for manual configuration or prior knowledge of frequency relationships, significantly improving ease of operation while avoiding the complexity of manual frequency detection circuits.
Solution Approach 2:
The synchronizing device incorporates feedback mechanisms that continuously monitor the clock signal frequencies and adjust the synchronization process accordingly. This feedback-based operation allows the device to adapt to varying frequency conditions in real-time, improving operational convenience without requiring complex pre-detection circuits.
3Reliability
If the frequency of the first clock signal is faster than the second clock signal, then additional circuits are required for frequency conversion, but this increases hardware costs
Solution Approach 1:
The patent designs a universal synchronizing circuit that can handle both cases where the first clock signal is faster or slower than the second clock signal using the same basic structure. The device automatically adapts its operation based on the detected frequency relationship, eliminating the need for separate frequency conversion circuits for different operating conditions and thereby reducing hardware complexity while maintaining synchronization accuracy.
Solution Approach 2:
The synchronizing device incorporates dynamic adjustment capabilities that allow it to adapt its internal operation based on the real-time frequency relationship between clock signals. When the first clock signal is faster, the device dynamically adjusts its sampling and holding operations to maintain synchronization without requiring additional fixed-frequency conversion circuits, thus reducing hardware complexity while preserving reliability.
Data Source
AI summary
A signal synchronizing device includes a trigger module for capturing an input signal according to a first clock signal which corresponds with the input signal so as to generate a trigger signal, a storage unit for forming a first pulse signal by pulling an output thereof to a first logic level according to the trigger signal, and by pulling the output thereof to a second logic level according to a feedback reset signal, and a synchronizing module for performing synchronous transfer according to the first pulse signal so as to output an output signal corresponding with frequency of a second clock signal, and for generating the feedback reset signal according to the output signal.