Shared Memory Bus Controller for SDRAM and Flash Pin Reduction
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Solution Overview
Problem
In digital signal processing systems, the use of both synchronous DRAM and flash memory together requires a large number of pins for independent connections, leading to increased package size and substrate size, which is a challenge for device integration and cost reduction.
Innovation Solution
A memory bus shared system that allows simultaneous access to both synchronous and asynchronous memories using a controller with shared address and data terminals, optimizing protocol to avoid competition and ensure data transfer efficiency and rate without increasing pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SDRAM and flash memory are connected entirely individually or independently, then the access time and data transfer efficiency for both memories are guaranteed, but the pin number of the controller increases and the package size becomes larger
Solution Approach 1:
The patent merges the address buses and data buses of SDRAM and flash memory into a shared bus system. The controller uses a common address bus (AB0-AB19) and common data bus (DB0-DB15) to access both memory types, reducing the pin count from 67 to 35 while maintaining reliable access through protocol optimization that prevents bus conflicts.
Solution Approach 2:
The controller is designed with multi-functional capability to manage both synchronous SDRAM and asynchronous flash memory through universal bus interfaces. The same address and data terminals serve dual purposes for different memory types, eliminating the need for separate dedicated connections while preserving full access functionality.
2Device complexity
If the pin number of the controller is reduced by sharing buses, then the package size and substrate size decrease, but the data transfer efficiency and rate may be compromised due to bus competition
Solution Approach 1:
The patent implements dynamic bus arbitration where the controller adaptively manages bus access based on memory type and operation requirements. During SDRAM operations, the bus operates in synchronous mode with continuous data transfer, while during flash memory operations, it switches to asynchronous mode, optimizing data transfer rates for each memory type despite shared bus constraints.
Solution Approach 2:
The controller employs periodic time-division multiplexing to alternate between SDRAM and flash memory access operations. By carefully timing the switching between memory types and utilizing SDRAM's burst transfer capability, the system maintains high overall data transfer efficiency while preventing bus conflicts.
3Ease of manufacture
If the controller accesses both synchronous and asynchronous memories simultaneously, then the system integration is improved and assembly cost decreases, but the bus competition between memories increases
Solution Approach 1:
The controller acts as an intermediary that mediates all access requests to both SDRAM and flash memory through the shared bus. It implements intelligent arbitration logic that prevents bus conflicts by ensuring only one memory operation occurs at a time, managing the competition dynamically while simplifying the overall system architecture and reducing assembly complexity.
Data Source
AI summary
The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an SDRAM, immediately after that, access to FLASH is started, and a shared bus controller outputs the write/read address with respect to FLASH on the address bus. Then, after the end of data transfer on the data bus, either the shared bus controller outputs the write data, or FLASH can output the read data on the data bus by means of a strobe signal. Then, the input of address is established by FLASH, and, as the shared bus controller asserts a strobe signal, either FLASH fetches the write data on the data bus, or the shared bus controller fetches the read data on the data bus.