Clock Signal Generator for CDR Synchronization During Transmission Pauses
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Solution Overview
Problem
In communication systems, existing methods for reducing power consumption during data transmission pauses result in inefficiencies due to the time required for DC potential to return and CDR synchronization in the receiving apparatus, and transmitting invalid data during pauses still consumes power.
Innovation Solution
A transmission apparatus that generates a first clock signal for data transmission and a second clock signal with lower frequency during pauses, embedding the clock signal or synchronization signal to maintain CDR synchronization, allowing for reduced power consumption while keeping the receiving apparatus synchronized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the transmission apparatus stops signal transmission during a pause period to reduce power consumption, then power consumption is reduced, but CDR synchronization cannot be maintained in the receiving apparatus
Solution Approach 1:
The patent extracts the essential function of maintaining CDR synchronization from continuous data transmission by transmitting only synchronization signals during pause periods, separating the synchronization maintenance function from data transmission
Solution Approach 2:
The patent applies periodic transmission of synchronization signals during pause periods to maintain CDR lock in the receiving apparatus, using periodic pulses to keep the synchronization circuit active without continuous data transmission
2Reliability
If the transmission apparatus transmits invalid data during a pause period to maintain CDR synchronization, then CDR synchronization is maintained, but power consumption is not reduced
Solution Approach 1:
The patent transmits only the necessary synchronization signals at reduced frequency during pause periods, avoiding excessive transmission of invalid data while still maintaining CDR lock in the receiving apparatus
Solution Approach 2:
The patent changes the transmission parameters during pause periods by reducing the clock signal frequency and transmitting only synchronization signals instead of full data streams, achieving both power savings and synchronization maintenance
3Productivity
If the transmission apparatus resumes signal transmission after a pause period, then data transmission can continue, but DC potential takes time to return to the correct level
Solution Approach 1:
The patent transmits synchronization signals during the pause period before full data transmission resumes, preparing the receiving apparatus's CDR circuit in advance so that DC potential recovery and synchronization are already underway by the time data transmission restarts
Data Source
AI summary
There is provided a transmission apparatus including a clock signal generator that generates a clock signal and a transmitter that operates on the basis of the clock signal and transmits data in which the clock signal is embedded or a synchronization signal for maintaining CDR synchronization, in which during a period of data transmission, the clock signal generator generates a first clock signal for data transmission and the transmitter transmits data in which the first clock signal is embedded on the basis of the first clock signal, and during a pause period of data transmission, the clock signal generator generates a second clock signal having a frequency lower than that of the first clock signal and the transmitter transmits the synchronization signal on the basis of the second clock signal.