Dithered Pulse Phase Interpolation for Audio Clock Synthesis
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Solution Overview
Problem
Conventional methods for generating an audio clock signal from a higher frequency video clock signal are costly and resource-intensive, particularly in digital circuits like FPGAs, due to the need for phase-locked loops, numerically controlled oscillators, and application-specific signal processors, which are not efficiently utilized for handling multiple channels.
Innovation Solution
A clock signal generator that employs a dithered clock signal and phase interpolation to produce a synchronized audio clock signal, using a fractional phase accumulator, overflow logic, and a phase controller to delay the dithered pulse, allowing for the generation of a rational but non-integer submultiple of the input clock signal without requiring traditional clock-producing elements like VCOs or NCOs, thus leveraging commonly available FPGA resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL techniques with VCO are used to generate audio clock from video clock, then frequency synchronization is achieved, but device complexity and cost increase significantly
Solution Approach 1:
The patent replaces the mechanical/analog PLL system with a purely digital implementation. Instead of using a VCO and analog feedback loop, the invention uses digital logic circuits including counters, multiplexers, and phase detectors to achieve frequency division and synchronization. This substitution of digital logic for analog mechanisms reduces device complexity while maintaining frequency synchronization reliability.
Solution Approach 2:
The patent divides the frequency generation task into separate functional modules: an integer division counter for the integer part of the frequency ratio, and a fractional phase accumulation mechanism for the fractional part. This segmentation allows each module to handle a specific portion of the frequency division, simplifying the overall design compared to a monolithic VCO-based approach.
2Reliability
If NCO with DAC and analog filter are used, then audio clock generation is possible, but board space and product cost increase
Solution Approach 1:
The patent eliminates the need for DAC and analog filters by using purely digital logic to generate the audio clock signal. The digital implementation uses counters and phase accumulation circuits that can be implemented directly in FPGA or programmable IC resources, removing the requirement for external analog components and reducing board space occupancy.
Solution Approach 2:
The patent creates a digital copy of the clock generation function that replicates the timing characteristics without requiring physical analog components. By implementing the NCO functionality through digital arithmetic operations and phase accumulation, the system produces an equivalent clock signal that fits within standard digital logic resources.
3Adaptability or versatility
If multiple PLLs are used to handle multiple audio channels, then multiple clock signals can be generated, but the number of required PLL resources exceeds what is typically available in an FPGA
Solution Approach 1:
The patent designs a universal clock generation module that can be instantiated multiple times within a single FPGA to handle multiple audio channels. Each instance of the module uses the same digital logic structure, allowing flexible configuration for different frequency ratios and channels without requiring dedicated PLL hardware for each channel. This multi-functional design enables one FPGA resource to serve multiple purposes.
Solution Approach 2:
The patent combines the functions of multiple clock generation operations into a single integrated digital logic structure. By merging the integer division and fractional phase accumulation operations into one unified counter-based system, the design eliminates the need for separate PLLs for each channel, reducing the total number of required resources while maintaining multi-channel capability.
Data Source
AI summary
An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The rational submultiple includes an integer part and a fractional part, the fractional part including a numerator and a denominator. A dithered pulse generator is configured to produce the dithered pulse signal from a count of the reference clock signal that is reset dependent on the integer part, and a fractional phase signal from a count that is incremented by the numerator and that is reset dependent on the denominator. A phase controller is configured to delay the dithered pulse with a delay proportional to the fractional phase to produce the output clock signal. The delay may be calibrated by internal logic.