Clock Domain Data Transfer Using Transition-Aware Safety Detection
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Solution Overview
Problem
Existing methods for transferring data signals between unsynchronized clock domains of different frequencies are slow and power-consuming, requiring multiple synchronization cycles and the use of handshaking procedures that introduce delays and risk of data corruption.
Innovation Solution
A system and method that check if the receiving clock domain is away from a forthcoming transition using a comparator clocked by the faster clock domain, allowing data transfer only if the input signal is different, thereby avoiding synchronization delays and data corruption, and enabling faster and more efficient data transfer without the need for handshaking or busy flags.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If handshaking procedures are used to transfer data between unsynchronized clock domains, then data transfer safety is improved, but transfer time increases significantly
Solution Approach 1:
The patent extracts the safety check mechanism from the traditional handshaking procedure. Instead of requiring multiple synchronization cycles with busy flags, the invention uses a dedicated safety detection circuit that monitors the receiving clock domain's transition state independently. This allows data transfer to proceed as soon as safety is confirmed, without waiting for sequential handshaking acknowledgments, thereby reducing transfer time while maintaining data integrity.
Solution Approach 2:
The patent implements preliminary detection of the receiving clock domain's transition state before data transfer initiates. The safety detection circuit continuously monitors the receiving clock domain and prepares transfer enable signals in advance. When the receiving domain is in a safe state (away from transitions), the transmitter can immediately transfer data without entering a lengthy handshaking sequence, thus resolving the contradiction between safety and speed.
2Reliability
If handshaking procedures with busy flags are used, then data corruption is prevented, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming handshaking protocol (busy flags, multiple acknowledgment cycles) from the data transfer process. Instead, it employs a continuous but lightweight safety detection mechanism that monitors clock domain transition states. This detection circuit operates at minimal power while providing the same corruption prevention function, as it only requires monitoring clock signals rather than maintaining complex handshaking state machines that must remain active throughout the transfer process.
3Reliability
If source data is frozen during handshaking procedures, then data consistency is maintained, but transfer efficiency decreases
Solution Approach 1:
The patent performs preliminary safety detection and prepares transfer enable signals before data transfer begins. The safety detection circuit continuously monitors the receiving clock domain and has transfer readiness signals prepared in advance. This allows source data to remain dynamic and unchanged during transfer, as the safety mechanism is already in place and does not require freezing data sources. The transfer can proceed immediately when safety is detected, maintaining both data consistency and high transfer efficiency.
4Reliability
If multiple synchronization cycles are used between clock domains, then synchronisation reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the synchronization reliability function from complex multi-cycle handshaking sequences and implements it through a dedicated safety detection circuit. This circuit directly monitors the receiving clock domain's transition states and generates transfer enable signals based on real-time safety conditions. By replacing sequential handshaking with parallel safety monitoring, the invention achieves the same synchronization reliability with significantly reduced device complexity, as it eliminates the need for multiple state machines, busy flags, and acknowledgment protocols.
Data Source
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AI summary
A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).