Clock Generator Phase Synchronization for Dispersed Semiconductor Blocks
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Solution Overview
Problem
In semiconductor devices with dispersed data transfer blocks, the increased distance between blocks leads to longer clock tree lengths and larger clock jitter, making it difficult to synchronize the phases of frequency-divided PLL clocks across multiple blocks.
Innovation Solution
A clock generator is used to control the phases of frequency-divided PLL clocks based on a common start signal, ensuring that the phases of these clocks are synchronized across all data transfer blocks, thereby reducing clock jitter and achieving the required command-data interval in DDR-PHY operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data transfer blocks are dispersed to increase layout flexibility, then layout flexibility is improved, but clock jitter increases due to longer clock tree lengths
Solution Approach 1:
The patent divides the DDR-PHY into multiple dispersed data transfer blocks, each with its own local PLL circuit. This segmentation allows each block to have an independent clock source, reducing the impact of long clock tree lengths on overall clock jitter while maintaining layout flexibility.
Solution Approach 2:
Each data transfer block is equipped with a local PLL circuit that generates clocks locally rather than relying on a centralized clock source. This local quality approach ensures that each block has optimized clock characteristics independent of its distance from other blocks, reducing clock jitter despite dispersion.
2Reliability
If local PLL circuits are added to each data transfer block to reduce clock jitter, then clock jitter is reduced, but phase synchronization becomes difficult
Solution Approach 1:
The patent employs a feedback mechanism where the clock generator receives a start signal and controls the phases of frequency-divided PLL clocks based on this common input. This feedback approach ensures that all local PLL circuits maintain synchronized phases despite being physically dispersed, resolving the synchronization difficulty without compromising clock jitter reduction.
3Adaptability or versatility
If the distance between data transfer blocks increases, then layout flexibility is improved, but clock tree length increases leading to larger clock jitter
Solution Approach 1:
By segmenting the clock generation function into local PLL circuits at each data transfer block, the patent eliminates the need for long centralized clock trees. Each block generates its own clocks locally, so the physical distance between blocks no longer impacts clock tree length, allowing greater layout flexibility.
Data Source
AI summary
The present invention solves a problem that the phases of clocks obtained by frequency-dividing PLL clocks output from local PLL circuits cannot be made the same in a plurality of data transfer blocks. A local PLL circuit outputs a PLL clock obtained by multiplying a common external clock. A frequency divider outputs a feedback clock obtained by frequency-dividing the PLL clock to the local PLL circuit. An FIFO buffer temporarily holds data input from the outside. The FIFO buffer outputs the held data on the basis of a frequency-divided PLL clock. A clock generator generates a frequency-divided PLL clock obtained by frequency-dividing the PLL clock. The clock generator controls the phase of the frequency-divided PLL clock on the basis of a common start signal.