Gating Circuit for Memory Timing Signal Filtering
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Solution Overview
Problem
Current memory controller systems face challenges in accurately timing read operations with memory devices, particularly in filtering out noise and ensuring reliable data transfer, as existing solutions struggle to effectively manage the gating of timing signals to prevent mistriggers and data corruption.
Innovation Solution
A system and method that utilize a gating circuit to filter timing signals by opening and closing a gating window based on a control signal, with the timing control circuit generating the control signal to align the gating window with the preamble portion of the timing signal, ensuring that only valid data transfer regions are passed through, thereby eliminating tri-state regions that can cause glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gating circuit opens the gating window early to capture the timing signal, then the reliability of read operations is improved by preventing mistriggers, but noise and undesirable regions may be included in the filtered timing signal
Solution Approach 1:
The gating window is opened during the preamble portion of the timing signal before the valid data transfer region begins. This preliminary action allows the system to prepare for data capture while filtering out tri-state regions that cause glitches, thereby improving reliability without capturing excessive noise
Solution Approach 2:
The gating circuit acts as an intermediary between the timing signal from the memory device and the memory controller. It selectively passes through only the valid portions of the timing signal during the gating window, filtering out both tri-state regions and noise while maintaining signal integrity
2Reliability
If the gating window is opened during the preamble portion of the timing signal, then tri-state regions causing glitches are eliminated, but the timing precision for data capture must be precisely controlled
Solution Approach 1:
The control signal is delayed to cause the gating window to open during the preamble portion of the timing signal, before the valid data transfer region. This preliminary timing action eliminates tri-state regions that cause glitches while the counter and delay circuitry ensure precise timing control
Solution Approach 2:
The patent replaces manual timing adjustment with an automated counter and delay circuit system. The counter triggered by the control signal automatically determines when to close the gating window based on the falling edge of the timing signal, eliminating the need for manual timing precision adjustments
3Reliability
If the gating window is closed based on a falling edge determined by a counter, then accurate data transfer is ensured, but the device complexity increases due to additional control circuits
Solution Approach 1:
The gating circuit uses the timing signal's own falling edge, detected by a counter triggered by the control signal, to automatically close the gating window. This self-service mechanism ensures accurate data transfer by synchronizing the gate closure with the actual signal characteristics without requiring external control
Solution Approach 2:
The counter monitors the falling edge of the timing signal and provides feedback to close the gating window at the appropriate time. This feedback mechanism ensures that the gating window is closed precisely when needed for accurate data transfer while using a relatively simple counter-based approach
Data Source
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AI summary
Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a failing edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal.