Clock Source Frequency Transition Control for Memory Stability
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Solution Overview
Problem
Conventional power management designs for memory devices fail to swiftly adjust clock frequencies, leading to instability and unavailability of memory access during frequency changes, which can result in system malfunctions and power inefficiencies.
Innovation Solution
A frequency hopping scheme is employed by the clock generator to maintain a frequency-locked state during transitions, using a processor to calibrate memory controller parameters and enable smooth or piecewise frequency changes, ensuring continuous memory access and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock frequency of the memory device is reduced to decrease power consumption, then power consumption is reduced, but the system is unable to access the memory device during frequency transition
Solution Approach 1:
The patent applies preliminary action by performing frequency calibration of the memory controller before the actual frequency transition occurs. The processor calibrates the memory controller parameter under the new clock frequency in advance, so that when the frequency transition completes, the memory controller is already ready to operate correctly, ensuring continuous memory access availability without system malfunction.
Solution Approach 2:
The patent implements dynamics by transitioning the clock frequency in a controlled, dynamic manner rather than a static switch. The frequency hopping scheme allows the controllable clock source to transition between frequencies while maintaining a frequency-locked state, enabling smooth frequency changes that preserve memory access availability throughout the transition process.
2Loss of energy
If conventional power management design changes clock frequency, then power consumption is reduced, but the PLL leaves frequency-locked state causing instability
Solution Approach 1:
The patent uses dynamics by implementing a frequency hopping scheme that enables the controllable clock source to change frequency while maintaining the frequency-locked state. This dynamic approach allows the PLL to adapt to frequency changes without losing lock, ensuring stability throughout the transition process.
Solution Approach 2:
The patent applies parameter changes by adjusting the memory controller parameter through calibration under different clock frequencies. The processor calibrates the parameter to find optimal settings for each frequency, allowing the system to maintain stable operation across frequency transitions by adapting control parameters rather than relying solely on fixed PLL settings.
3Productivity
If the memory device operates at highest clock frequency, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamics by enabling dynamic frequency adjustment of the memory device. The system can operate at the highest clock frequency when high productivity is needed and transition to lower frequencies when power consumption needs to be reduced, providing flexible adaptation between performance and power efficiency requirements.
Solution Approach 2:
The patent applies parameter changes by allowing the clock frequency parameter to be dynamically adjusted based on computational workload requirements. The frequency hopping scheme enables the system to switch between different frequency operating points, optimizing the balance between productivity and power consumption according to real-time needs.
Data Source
AI summary
An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.