Memory Chip MR Register Programming via Parallel ID Segmentation
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Solution Overview
Problem
Prior art memory bus MR register programming approaches fail to accurately target and configure memory chips during system boot-up due to timing constraints, leading to potential misinterpretation of commands by memory chips before the DQ signal lines are fully trained.
Innovation Solution
The implementation of a parallel programming method for Local_ID and Target_ID registers, allowing memory chips to be uniquely identified and configured with relaxed timing constraints, ensuring accurate command execution by only activating the relevant memory chips with matching Local_ID and Target_ID values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sequential MR register programming is used during system boot-up, then the programming process can be completed, but the timing constraints cause commands to be misinterpreted by memory chips before DQ signal lines are fully trained
Solution Approach 1:
The patent applies preliminary action by programming the Local_ID register into each memory chip before the main MR register programming process begins. This preliminary identification phase allows the system to establish unique identifiers for each chip while the DQ signal lines are still being trained, preventing subsequent command misinterpretation. The Local_ID programming occurs during the training phase itself, rather than waiting for training to complete, thus resolving the timing constraint issue.
Solution Approach 2:
The patent segments the MR register programming process into two distinct phases: (1) preliminary Local_ID register programming that occurs during DQ signal line training, and (2) subsequent Target_ID and MR register programming that occurs after training completes. This segmentation allows different parts of the programming process to operate under appropriate timing conditions, with identification happening early and configuration happening later, thereby eliminating command misinterpretation while maintaining efficient boot-up timing.
2Reliability
If relaxed timing constraints are applied to allow accurate command execution, then command interpretation accuracy improves, but the programming process becomes slower
Solution Approach 1:
The patent performs the identification function (Local_ID programming) in advance during the training phase when timing constraints are naturally more relaxed, before proceeding to the configuration phase (Target_ID and MR register programming). This preliminary action ensures accurate command execution for the critical identification step without compromising overall programming speed, as the time-consuming accurate programming is done in parallel with signal line training.
Solution Approach 2:
The patent dynamically adjusts the timing constraints based on the programming phase. During the Local_ID programming phase, relaxed timing constraints are applied to ensure accurate command execution. During subsequent MR register programming phases, optimized timing constraints are used to maximize programming speed. This dynamic adaptation of timing constraints to match the specific requirements of each programming stage resolves the contradiction between accuracy and speed.
3Measurement precision
If unique identification of each memory chip is implemented, then accurate targeting and configuration is achieved, but the device complexity increases
Solution Approach 1:
The patent segments the identification and configuration functions into separate register structures: Local_ID register for unique chip identification and Target_ID/MR registers for configuration. This segmentation allows each register type to have a specialized, simplified programming sequence. The Local_ID programming uses a simple write operation during training, while Target_ID programming follows a standardized sequence after training, reducing overall complexity compared to a single unified programming mechanism.
Solution Approach 2:
The patent introduces the Local_ID register as an intermediary structure that facilitates accurate chip identification without directly complicating the main MR register programming process. The Local_ID serves as a preliminary identifier that simplifies subsequent Target_ID programming by establishing a known reference point. This intermediary structure enables precise chip targeting while maintaining relatively simple programming sequences through the use of standardized command protocols.
Data Source
AI summary
A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.