One-Wire Bus Manchester Encoding for High-Speed RF Control

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Solution Overview

Problem

Existing serial communication technologies, such as I2C, I3C, SPMI, and RFFE, face challenges with increased demand for GPIO pins and communication link throughput due to device complexity and stringent timing constraints, particularly in mobile communication devices, where conventional one-wire bidirectional communication buses are limited by slow data rates and unsuitable for high-speed RF-Front End control applications.

Innovation Solution

Implementing a single-wire link using Manchester encoding and synchronization signaling to maintain clock synchronization between transmitting and receiving devices, allowing for bidirectional communication with data rates up to 52 MHz by embedding clock information in data transmissions and using modified control signaling to manage transactions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional one-wire bidirectional communication buses are used, then the number of GPIO pins is reduced, but the data rate becomes too slow for high-speed RF-Front End control applications

Engineering Contradiction:
Improvenumber of GPIO pinsVSAvoiddata rate
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent merges the clock signal and data transmission into a single wire by embedding clock information within the data transmissions using Manchester encoding. This combining of synchronization and data functions into one channel enables high-speed communication (up to 52 MHz) while maintaining the space-saving advantage of a one-wire interface, thus resolving the contradiction between reducing GPIO pins and achieving high data rates.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the encoding parameters by implementing Manchester encoding with specific transition rules (rising edge for logic 0, falling edge for logic 1) and defines new control signaling parameters (sequence start conditions, arbitration mechanisms). These parameter changes enable the one-wire interface to achieve timing precision and data rates suitable for high-speed RF-Front End control, overcoming the speed limitation of conventional one-wire buses.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If multiple concurrent RF links are supported, then communication capability is improved, but inter-device interference increases

Engineering Contradiction:
Improveconcurrent RF links supportVSAvoidinter-device interference
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements a coexistence management mechanism that performs preliminary arbitration and scheduling before actual data transmission. Devices register their communication requirements in advance, and the system allocates time slots and resources beforehand, preventing conflicts and interference during concurrent RF link operations. This preliminary coordination enables multiple RF links to operate simultaneously without harmful interference.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If Manchester encoding with embedded clock information is used, then clock synchronization is maintained, but signaling complexity increases

Engineering Contradiction:
Improveclock synchronizationVSAvoidsignaling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-synchronizing Manchester encoding where each data bit contains embedded clock information through mid-bit transitions. The receiving device automatically extracts clock timing from the data signal itself without requiring a separate clock line or complex external synchronization circuitry. This self-service approach maintains reliable clock synchronization while keeping the signaling implementation relatively simple and integrated within the existing one-wire interface.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4483268B1One-wire bidirectional bus signaling with manchester encoding
Publication Date: 2026.02.18 QUALCOMM INC
  • EP4483268B1 patent drawingFigure 1
  • EP4483268B1 patent drawingFigure 2
  • EP4483268B1 patent drawingFigure 3

AI summary

An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.