Multi-clock control for managing frequency transients
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Solution Overview
Problem
The challenge lies in efficiently managing the clock frequency of processing units to balance performance and power consumption, as switching between clock generators can result in large frequency gaps leading to voltage droop and current transients, while constraining these gaps reduces the dynamic frequency range.
Innovation Solution
A method involving multiple settings for clock generators with adjustable maximum and minimum frequencies allows for dynamic frequency adjustments by switching between these settings based on power budget conditions, enabling efficient performance without exceeding power limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If switching between clock generators with large frequency gaps is used to cover a wide frequency range, then the dynamic frequency range is improved, but voltage droop and current transients occur
Solution Approach 1:
The system dynamically adjusts the frequencies of both clock generators based on operating conditions. The controller modifies the frequency of the first clock generator to be closer to the second clock generator's frequency when switching, thereby reducing the frequency gap and minimizing voltage droop and current transients while still achieving the desired frequency range coverage.
Solution Approach 2:
The patent changes the frequency parameters of the clock generators adaptively. By adjusting the frequency of the first clock generator based on the selected frequency of the second clock generator and current operating conditions, the system optimizes the frequency transition to avoid large gaps that cause electrical disturbances, thus resolving the contradiction between wide frequency range and system stability.
2Reliability
If constraining the frequency gap between clock generators is used to reduce voltage droop and current transients, then system stability is improved, but the dynamic frequency range is reduced
Solution Approach 1:
The system employs dynamic frequency adjustment where the controller continuously monitors operating conditions and modifies the frequency of the first clock generator accordingly. This dynamic approach allows the system to maintain small frequency gaps for stability when needed, while still achieving a wide overall frequency range by sequentially adjusting frequencies based on workload requirements.
Solution Approach 2:
The controller pre-adjusts the frequency of the first clock generator before switching occurs, based on the anticipated frequency needs and current system state. This preliminary adjustment ensures that the frequency gap remains manageable, preventing voltage droop and current transients, while still enabling the system to access a wide frequency range over time through controlled adjustments.
3Productivity
If increasing clock frequency is used to improve application execution speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The system dynamically selects and adjusts clock frequencies based on real-time power budget conditions and application requirements. The controller monitors power consumption and execution speed, adjusting the clock frequency to achieve the optimal balance - increasing frequency when power budget allows for improved productivity, and reducing frequency when power constraints are approached, thus resolving the contradiction between speed and energy efficiency.
Solution Approach 2:
The patent implements adaptive parameter changes by modifying the clock frequency based on power budget conditions. The controller adjusts the frequency parameter dynamically, increasing it to improve application execution speed when power is available, and decreasing it when power consumption approaches the budget limit, thereby optimizing both productivity and energy efficiency according to system state.
Data Source
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AI summary
Two clocks, a fast clock and a slow clock are provided for clocking a processing unit. A plurality of frequency settings, referred to as gears, are defined for the two clock. Each of these gears indicates a maximum frequency for the fast clock and a minimum frequency for the slow clock, such that the gap between the two frequencies may be kept to a manageable level so as to reduce transients upon switching between the two clocks. The system switches between the gears as required. In response to a determination to increase the frequency of the clock signal, a higher gear is selected at which the maximum and minimum frequencies defined for that gear are higher than the previous selected gear. Likewise, in response to a determination to decrease the frequency of the clock signal, a lower gear is selected, at which the maximum and minimum frequencies defined for that gear are lower than the previous selected gear.