Lockstep Processing Power Gating for Fault Detection

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Solution Overview

Problem

Current methods for enhancing the reliability of data processing devices, such as redundant components at the Register Transfer Level and radiation hardening, either compromise performance or increase design and manufacturing costs, failing to provide a balanced solution for safety-critical equipment.

Innovation Solution

The implementation of a lockstep processing system that power gates a subset of cores between a primary and secondary power source, allowing for fault detection and error correction through error detection circuitry, while maintaining performance and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant components at Register Transfer Level are used to increase reliability, then reliability is improved, but performance deteriorates and design costs increase

Engineering Contradiction:
ImprovereliabilityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system segments the power supply to different core groups, allowing independent power gating control. This enables fault detection by comparing outputs from cores powered by different sources without requiring full system redundancy, thus improving reliability while maintaining performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary power gating mechanism that selectively powers different core groups from different power sources. This intermediary layer enables fault detection and isolation without requiring complete redundant processing paths, resolving the contradiction between reliability and performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If radiation hardening process technology is used to increase reliability, then reliability is improved, but manufacturing costs increase

Engineering Contradiction:
ImprovereliabilityVSAvoidmanufacturing costs
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the operational parameters of existing cores by dynamically controlling their power sources through power gating. Instead of modifying the physical structure through expensive rad-hard processes, the system achieves reliability by changing how cores are powered and monitored, thereby improving reliability while avoiding increased manufacturing costs.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If power gating between primary and secondary power sources is implemented, then fault detection capability is improved, but device complexity increases

Engineering Contradiction:
Improvefault detection capabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides cores into different groups that can be independently powered from primary or secondary sources. This segmentation enables fault detection by comparing results from differently powered groups without requiring complex full-system redundancy, thus improving fault detection while controlling complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power gating mechanism serves multiple functions: it enables fault detection, provides fault isolation, and maintains system operation. This multi-functionality reduces the need for separate dedicated fault detection hardware, thereby improving reliability without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10725873B2Lockstep processing systems and methods
Publication Date: 2020.07.28 ARM LTD
  • US10725873B2 patent drawing
  • US10725873B2 patent drawing
  • US10725873B2 patent drawing

AI summary

The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.