Proxy Clock Network Power Estimation for IC Design
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Solution Overview
Problem
The design of integrated circuits faces challenges in estimating the power behavior of clock networks during the logical design phase without completing the full implementation-quality synthesis process, which is time-consuming and not feasible for exploring multiple design variations.
Innovation Solution
A reduced clock synthesis process is applied to generate a proxy clock network that estimates power behavior more quickly by relaxing certain design constraints, such as clock skew and buffer count, allowing for faster power estimation while maintaining similar power behavior to the fully synthesized clock network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the full implementation-quality clock synthesis process is used to estimate power behavior, then the accuracy of power estimation is improved, but the design time and compute resources required increase significantly
Solution Approach 1:
The clock synthesis process is segmented into two distinct approaches: a reduced clock synthesis process for rapid power estimation and a full implementation-quality clock synthesis process for final accurate results. The reduced process handles only the essential steps needed for power estimation, separating it from the complete synthesis workflow, thereby enabling fast exploration of design variations without sacrificing the option for accurate final estimation.
Solution Approach 2:
The reduced clock synthesis process performs only the necessary subset of operations required for power estimation, applying partial action rather than the complete synthesis process. This includes generating a proxy clock network with relaxed constraints on certain parameters like clock skew and buffer count, which is sufficient for power estimation purposes but would be inadequate for final implementation, thus achieving fast results with acceptable accuracy for exploration phases.
2Productivity
If the reduced clock synthesis process is used to generate proxy clock network, then the design exploration efficiency is improved, but the manufacturing precision of clock network parameters deteriorates
Solution Approach 1:
Different quality levels are applied to different aspects of the clock network. The proxy clock network maintains sufficient accuracy for power estimation purposes while relaxing constraints on parameters like clock skew and buffer count. This local quality approach ensures that the critical aspect (power estimation accuracy) is preserved while non-critical aspects (exact clock skew, buffer placement) are simplified, enabling fast design exploration.
Solution Approach 2:
A proxy clock network is created as a simplified copy of the full clock network for power estimation purposes. This copy replicates the essential structure and power-relevant characteristics while omitting detailed optimization, allowing rapid evaluation of design variations without requiring the complete, time-consuming synthesis process.
3Reliability
If multiple design variations are explored during front-end design, then the design quality is improved, but the compute resources and time required increase
Solution Approach 1:
Power estimation is performed preliminarily during the front-end design phase using the reduced clock synthesis process, before committing to a final design. This preliminary action allows designers to evaluate multiple design variations and make informed decisions early in the design process, avoiding the need to perform computationally expensive full synthesis on every variation, thus conserving compute resources while maintaining design quality.
Data Source
AI summary
An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.