Glitch-Free Clock Domain Crossing via Synchronization Registers
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Solution Overview
Problem
Current System-on-a-chip (SoC) designs face challenges in verifying glitch-free clock domain crossing signals due to metastability issues, setup and hold-time violations, and unpredictable delays across clock domains, which traditional Register Transfer Level (RTL) functional simulation techniques are insufficient to address, and static timing analysis is prone to errors and manual inspection.
Innovation Solution
A method involving the identification of output signals driving domain crossing logic, where a register is attached to the domain crossing logic to receive an output signal and a synchronization signal, preventing signal transitions at selected clock cycle intervals, and using formal verification and sequential equivalence checking to ensure glitch-free crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional RTL functional simulation techniques are used for CDC verification, then the verification process is simple and familiar, but it is insufficient to identify metastability issues and analog effects at transistor level
Solution Approach 1:
The patent introduces an intermediary verification methodology that bridges RTL simulation and transistor-level analysis. This intermediary layer uses enhanced simulation techniques with controlled clock domain configurations to detect metastability issues without requiring full transistor-level complexity, thus resolving the contradiction between verification reliability and methodology complexity.
Solution Approach 2:
The patent applies preliminary action by performing static timing analysis and setting up specific test conditions before actual CDC verification. This preliminary preparation identifies potential metastability issues early, allowing the verification process to focus on critical paths without requiring exhaustive transistor-level simulation of the entire system.
2Measurement precision
If static timing analysis is used for CDC verification, then timing violations can be identified, but it requires manual inspection and is prone to errors
Solution Approach 1:
The patent implements feedback mechanisms where verification results automatically trigger corrections to timing constraints and analysis parameters. The system uses iterative verification loops where detected issues feed back into refining the static timing analysis setup, reducing manual inspection requirements and minimizing human error while maintaining high detection precision.
Solution Approach 2:
The patent replaces manual inspection mechanisms with automated verification algorithms that use machine learning and heuristic approaches to interpret timing analysis results. This substitution eliminates human error in manual inspection while maintaining the precision of timing violation detection through automated pattern recognition.
3Reliability
If gate-level simulation is performed to find timing violations, then specific violations can be detected, but it may miss other potential violations in various CDC paths and fixes at late stages are risky
Solution Approach 1:
The patent segments the CDC verification process into multiple independent analysis passes, each focusing on specific clock domain crossing paths. This segmentation allows comprehensive coverage of all CDC paths without requiring exhaustive simulation of the entire system at gate level, reducing verification time while maintaining detection reliability through targeted analysis of critical segments.
Solution Approach 2:
The patent performs preliminary identification of critical CDC paths using static analysis before conducting gate-level simulation. This preliminary action focuses computational resources on high-risk paths, enabling detection of timing violations early in the design process and allowing corrections before late-stage implementation, thus reducing iterative redesign time.
4Speed
If combinatorial logic is used in domain crossings to meet performance goals, then performance requirements are satisfied, but glitches from combinatorial logic output may cause timing violations at the receiver
Solution Approach 1:
The patent introduces intermediary synchronization registers and control logic between combinatorial logic stages in clock domain crossings. These intermediaries buffer and stabilize signals, preventing glitches from propagating to the receiver while maintaining the high performance enabled by combinatorial logic, thus resolving the contradiction between speed and signal stability.
Data Source
AI summary
A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.