Asynchronous Finite State Machines with Fork Join Logic
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Solution Overview
Problem
Synchronization across clocked finite state machines in digital circuit designs leads to significant power dissipation and increased design costs due to global clock distribution challenges.
Innovation Solution
A sequential asynchronous system comprising two asynchronous finite state machines operating at different clock rates, coupled with a fork and join logic circuit that generates and manages requests and acknowledgments to initiate state transitions, allowing independent operation and reducing dependency on a shared clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global clock is distributed across different circuits of the finite state machine, then synchronization between clocked finite state machines is achieved, but power dissipation increases significantly
Solution Approach 1:
The patent extracts the global clock distribution system from the architecture and replaces it with asynchronous finite state machines that operate independently without a shared clock signal. Each FSM uses its own local timing mechanisms, eliminating the need for extensive clock routing infrastructure and the associated power consumption.
Solution Approach 2:
The patent introduces fork and join logic circuits as intermediary components that mediate communication and synchronization between asynchronous FSMs. These intermediaries use handshake protocols and control signals to coordinate state transitions without requiring a global clock, thereby maintaining synchronization while avoiding the power costs of clock distribution.
2Reliability
If global clock distribution is addressed to achieve synchronization, then design challenges are met, but design costs increase
Solution Approach 1:
The patent removes the complex global clock distribution infrastructure from the design, replacing it with simpler asynchronous FSMs that don't require synchronized clock signals. This extraction eliminates numerous clock routing traces, buffer circuits, and synchronization elements, thereby reducing design complexity and manufacturing costs.
Solution Approach 2:
Each asynchronous FSM is self-sufficient, generating its own control signals and timing mechanisms without relying on a centralized clock source. The fork and join logic circuits autonomously manage coordination between FSMs using local handshake protocols, eliminating the need for expensive global synchronization infrastructure.
3Stability of the object's composition
If clocked finite state machines are used, then predictable sequence of events is executed, but power dissipation and design costs increase due to synchronization requirements
Solution Approach 1:
The fork and join logic circuits serve as mediators that ensure predictable sequencing of events across asynchronous FSMs. The fork logic generates control signals based on the current state of one FSM, and the join logic coordinates state transitions in another FSM, maintaining a predictable event sequence through structured handshaking rather than clock synchronization.
Solution Approach 2:
The asynchronous FSM architecture incorporates feedback mechanisms where the state of one FSM influences the control signals generated by fork logic, which in turn trigger state transitions in other FSMs through join logic. This feedback-based coordination ensures predictable sequencing without the power consumption of global clock distribution.
Data Source
AI summary
A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock rate and operating a second asynchronous finite state machine at a second clock rate. The method also includes generating, with fork logic, a fork request based on a first state of the first asynchronous finite state machine and receiving, with join logic, the fork request from the fork logic. The method further includes receiving, with the join logic, a communication request from the second asynchronous finite state machine based on a second state of the second asynchronous finite state machine and initiating, with the join logic, a state transition of the second asynchronous finite state machine. The method also includes providing, with the join logic, a join acknowledgement to the fork logic upon completion of the state transition.