Multiple-Queue Coalescing Mapping with Shared Base Timer
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Solution Overview
Problem
Computing systems face a trade-off between minimizing CPU interrupts and timely data processing due to interrupt coalescing, which introduces additional processing latencies, and existing methods do not efficiently allow users to tune coalescing settings to balance these factors.
Innovation Solution
An integrated circuit and method that set coalescing latencies for multiple data queues using user-defined values and a shared base timer, allowing users to configure network coalescing latencies efficiently by mapping these values to hardware registers, thereby tuning performance and reducing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interrupt coalescing is implemented to reduce CPU interrupts, then interrupt frequency is reduced, but data processing time increases due to additional latencies
Solution Approach 1:
The patent implements dynamic coalescing latency configuration where users can set different coalescing latency values for different data queues based on their specific performance requirements. The system dynamically adjusts the coalescing behavior by mapping user-defined latency values to appropriate hardware register settings, allowing optimization of the balance between interrupt frequency and processing time for each queue independently.
Solution Approach 2:
The patent changes the parameter of coalescing latency from fixed to configurable by users. By allowing users to define custom coalescing latency values and mapping these to hardware register values, the system enables parameter optimization to resolve the trade-off between reducing CPU interrupts and maintaining timely data processing.
2Adaptability or versatility
If separate timer registers are provided for each data queue to allow independent coalescing latency control, then user tuning capability is improved, but hardware complexity increases
Solution Approach 1:
The patent introduces a mapping component as an intermediary layer between the user-defined coalescing latency values and the hardware timer registers. This mapping component translates user-friendly latency specifications into the appropriate hardware register values, providing full user control without requiring users to directly manage complex hardware timer registers for each queue.
Solution Approach 2:
The patent implements a universal mapping mechanism that handles coalescing latency configuration for multiple data queues through a unified approach. The mapping component serves all queues independently while using a common base timer, reducing hardware complexity compared to having completely separate timer registers for each queue while maintaining full user tuning capability.
Data Source
AI summary
A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.