PCIe Clock Request Pad Power Saving via Multiplexer Control
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Solution Overview
Problem
Current PCIe devices cannot enter power-saving mode when mixed with old devices that do not support the clock request pin function, as the clock request pins remain at a low voltage level, preventing new devices from entering power-saving mode.
Innovation Solution
Incorporating a multiplexer and control circuit in the PCIe device to generate control signals for the clock request pad, allowing it to operate at a high voltage level for power-saving mode even without clock signal usage, and switching to a predetermined voltage level when the high voltage level cannot be achieved, enabling power-saving mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock request pin is shared across multiple PCIe devices on the motherboard, then all devices can use the same pin for clock requests, but new PCIe devices cannot enter power-saving mode when old devices keep the pin at low voltage level
Solution Approach 1:
The patent segments the clock request functionality by separating the detection of clock request intent from the actual clock request signal. The new PCIe device independently determines its power-saving mode based on its own operational state, rather than being constrained by the shared clock request pin state. This segmentation allows the device to ignore the pin state caused by old devices and make autonomous power management decisions.
Solution Approach 2:
The patent introduces an intermediary mechanism where the new PCIe device uses its own internal state or alternative signals to determine power-saving mode, rather than directly relying on the shared clock request pin. This intermediary approach allows the device to filter out the influence of old devices that cannot properly manage the shared pin, enabling independent power-saving decisions.
2Reliability
If the clock request pin remains at low voltage level to request clock signals, then clock signals are generated for devices needing them, but power-saving mode cannot be entered even when not needed
Solution Approach 1:
The patent implements a feedback mechanism where the PCIe device continuously monitors its own operational state and the actual need for clock signals, then autonomously adjusts its power mode accordingly. This feedback loop allows the device to accurately determine when to enter power-saving mode based on real-time operational requirements, rather than relying solely on the shared clock request pin state.
Solution Approach 2:
The patent changes the parameter used for power-saving mode determination from the shared clock request pin voltage level to an internal operational state parameter. This parameter change allows the device to make accurate power-saving decisions based on its own needs, independent of the voltage level on the shared pin which may be influenced by old devices.
3Use of energy by moving object
If all PCIe devices must set clock request pins to high voltage level to enter power-saving mode, then power-saving can be achieved, but devices needing clock signals cannot receive them
Solution Approach 1:
The patent segments the power management functionality so that each PCIe device independently manages its own power state based on its operational requirements. The new device can enter power-saving mode autonomously without requiring coordination with other devices through the shared clock request pin, eliminating the need for all devices to simultaneously set pins to high voltage level.
Solution Approach 2:
The patent enables the PCIe device to self-determine and self-manage its power-saving mode based on its own operational state. The device performs self-service by autonomously deciding when to enter or exit power-saving mode without being constrained by the states of other devices or the shared clock request pin, thereby maintaining both power efficiency and operational reliability.
Data Source
AI summary
An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.