Asymmetric Column Select Gates for Bitline Resistance Compensation
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in compensating for differences in bit line interconnection resistance, which can lead to read errors due to varying interconnection lengths and resistances, especially as design rules are reduced, affecting the timing margin of alternating current signals.
Innovation Solution
The semiconductor memory device incorporates first and second column select gates with different current drive abilities, sizes, and configurations to compensate for the differences in bit line interconnection resistance by adjusting their lengths and widths, ensuring that the current drive ability of the column select gate connected to the relatively long bit line is greater, thereby reducing the resistance disparity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the bit line interconnection length is increased, then the sensing range is expanded, but the bit line interconnection resistance increases causing read errors
Solution Approach 1:
The patent applies local quality by making the column select gates asymmetric - the first column select gate has a first size and the second column select gate has a second size different from the first size. This local differentiation compensates for the resistance difference caused by varying interconnection lengths, allowing the sensing range to be expanded while maintaining read accuracy.
2Productivity
If design rules are reduced to increase integration density, then the number of memory cells increases, but the timing margin of alternating current signals decreases
Solution Approach 1:
The patent changes the parameter of column select gate size to compensate for timing margin loss. By making the first column select gate have a first size and the second column select gate have a second size, the invention adjusts the drive strength to maintain adequate timing margins even as design rules are reduced and integration density increases.
3Ease of manufacture
If the interconnection length between bit line and column select gate is made equal, then manufacturing is simplified, but resistance compensation is lost
Solution Approach 1:
The patent deliberately introduces asymmetry by making the first column select gate have a first size and the second column select gate have a second size different from the first size. This asymmetric design compensates for the inherent resistance differences caused by unequal interconnection lengths, improving reliability while accepting the manufacturing complexity.
Data Source
AI summary
A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.