Semiconductor Conductive Bumps With Asymmetric Widths For Uniform Etching

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Solution Overview

Problem

In flip-chip packaging, the conventional under bump metal layer etching process results in uneven etching and bump deformation due to insufficient etchant penetration between closely spaced bumps, leading to incomplete removal and quality issues in semiconductor structures.

Innovation Solution

A conductive structure for semiconductor chips with alternately arranged first and second pads and under bump metal layers, featuring conductive bumps with varying widths, and a method involving a patterned insulation layer with specific opening widths to facilitate even etching and prevent deformation, ensuring complete removal of unnecessary under bump metal layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the spacing distance between bumps is reduced to increase circuit density, then the packaging volume is reduced and circuit density is increased, but the etchant cannot effectively permeate into the spacing distance causing uneven etching and bump deformation

Engineering Contradiction:
Improvecircuit densityVSAvoidetching uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The bump structure is segmented into two parts: a first bump portion with a first width and a second bump portion with a second width greater than the first width. This segmentation allows the etchant to access the spacing distance more effectively while maintaining the fine spacing for high circuit density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bump structure employs asymmetric width design where the second bump portion has a greater width than the first bump portion. This asymmetric configuration creates varying etching rates across different regions, enabling the etchant to penetrate the spacing distance effectively and achieve uniform etching overall.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If the etching process is performed to remove under bump metal layer, then the electrical conduction between chip components and external components is prevented, but the uneven etching causes bump deformation affecting quality

Engineering Contradiction:
Improveelectrical insulationVSAvoidbump shape integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Different portions of the bump structure are given different widths to create local quality variations. The first bump portion has a smaller width while the second bump portion has a larger width, allowing different etching rates in different regions to achieve both complete under bump metal layer removal and bump shape preservation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The bump width parameter is changed across different portions of the same bump structure. By varying the width parameter from the first bump portion to the second bump portion, the etching process can be controlled to achieve uniform etching and prevent deformation while ensuring electrical insulation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution allows for uniform etching and complete removal of under bump metal layers, preventing deformation and enhancing the quality of semiconductor structures by ensuring even etchant penetration and efficient bump formation.

Implementation Method 1

the etchant cannot effectively permeate into spacing distance 161... the reaction rate of the etchant in the wide area A2 is higher than the reaction rate of the etchant in the overlapping areas A1

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS8786109B2Conductive structure and method for forming the same
Publication Date: 2014.07.22 CHIPMOS TECH INC
  • US8786109B2 patent drawing
  • US8786109B2 patent drawing
  • US8786109B2 patent drawing

AI summary

A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.